Quadruple assignment

Discussion in 'VHDL' started by Merciadri Luca, Nov 1, 2010.

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    Hi,

    Say you define

    ==
    signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE := 0;
    ==

    where MAX_VALUE is a constant. My ghdl compiler will be okay with this
    statement, but what is its result? I would like to define sig1, sig2,
    sig3 and sig4 to be, initially, 0. But does that actually achieve what
    I want?

    Thanks.
    - --
    Merciadri Luca
    See http://www.student.montefiore.ulg.ac.be/~merciadri/
    - --

    Men are more moral than they think, and far more immoral than they can imagine. (Sigmund Freud)
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    Merciadri Luca, Nov 1, 2010
    #1
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  2. On Nov 1, 10:45 am, Merciadri Luca wrote:

    > ==
    > signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE := 0;
    > ==
    >
    > where MAX_VALUE is a constant. My ghdl compiler will be okay with this
    > statement, but what is its result?


    Each of your four signals has the same subtype
    (0 to MAX_VALUE). The explicit initialization ":=0"
    is redundant, because any VHDL variable or signal is
    initialized to the left-most value in its value set;
    in your case that value is 0 anyway. All four
    signals will have 0 as their initialization value.

    Note that the initial value is associated with
    the subtype part of the declaration. It is not
    attached to each individual data object; it
    applies to all four of them.

    > But does that actually achieve what I want?


    Only you can answer that :)
    --
    Jonathan Bromley
     
    Jonathan Bromley, Nov 1, 2010
    #2
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    Jonathan Bromley <> writes:

    > On Nov 1, 10:45 am, Merciadri Luca wrote:
    >
    >> ==
    >> signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE := 0;
    >> ==
    >>
    >> where MAX_VALUE is a constant. My ghdl compiler will be okay with this
    >> statement, but what is its result?

    >
    > Each of your four signals has the same subtype
    > (0 to MAX_VALUE). The explicit initialization ":=0"
    > is redundant, because any VHDL variable or signal is
    > initialized to the left-most value in its value set;
    > in your case that value is 0 anyway. All four
    > signals will have 0 as their initialization value.
    >
    > Note that the initial value is associated with
    > the subtype part of the declaration. It is not
    > attached to each individual data object; it
    > applies to all four of them.
    >
    >> But does that actually achieve what I want?

    Thanks. I did not know it! :)


    - --
    Merciadri Luca
    See http://www.student.montefiore.ulg.ac.be/~merciadri/
    - --

    In matters of style, swim with the current; in matters of principle, stand like a rock. (Thomas Jefferson)
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    Merciadri Luca, Nov 1, 2010
    #3
  4. Merciadri Luca

    rickman Guest

    On Nov 1, 8:09 am, Jonathan Bromley <>
    wrote:
    > On Nov 1, 10:45 am, Merciadri Luca wrote:
    >
    > > ==
    > > signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE := 0;
    > > ==

    >
    > > where MAX_VALUE is a constant. My ghdl compiler will be okay with this
    > > statement, but what is its result?

    >
    > Each of your four signals has the same subtype
    > (0 to MAX_VALUE).  The explicit initialization ":=0"
    > is redundant, because any VHDL variable or signal is
    > initialized to the left-most value in its value set;
    > in your case that value is 0 anyway.  All four
    > signals will have 0 as their initialization value.
    >
    > Note that the initial value is associated with
    > the subtype part of the declaration.  It is not
    > attached to each individual data object; it
    > applies to all four of them.
    >
    > > But does that actually achieve what I want?

    >
    > Only you can answer that :)
    > --
    > Jonathan Bromley


    That may be true for simulation, but for synthesis the initialization
    is often used for the initial value set during configuration. If the
    explicit assignment is omitted, will the synthesis tool match the
    simulation?

    Rick
     
    rickman, Nov 5, 2010
    #4
  5. On 11/5/2010 3:04 AM, rickman wrote:

    > That may be true for simulation, but for synthesis the initialization
    > is often used for the initial value set during configuration. If the
    > explicit assignment is omitted, will the synthesis tool match the
    > simulation?


    I would consider it unsafe to count on value of an internal register
    between power up configuration and system reset, for any target device.
    So I guess I see no reason to simulate it.


    -- Mike Treseler
     
    Mike Treseler, Nov 6, 2010
    #5
  6. Merciadri Luca

    rickman Guest

    On Nov 6, 5:14 pm, Mike Treseler <> wrote:
    > On 11/5/2010 3:04 AM, rickman wrote:
    >
    > > That may be true for simulation, but for synthesis the initialization
    > > is often used for the initial value set during configuration.  If the
    > > explicit assignment is omitted, will the synthesis tool match the
    > > simulation?

    >
    > I would consider it unsafe to count on value of an internal register
    > between power up configuration and system reset, for any target device.
    > So I guess I see no reason to simulate it.
    >
    >           -- Mike Treseler


    I'm not sure what your point is. Are you saying that you don't make
    use of the built in global reset function? That value matches the
    configuration reset value. Of course if you use logic to generate
    your own system reset you can set it to whatever you want independent
    of the configuration value. But that is out of context to what
    Jonathan was saying which is what I was replying to.

    Rick
     
    rickman, Nov 8, 2010
    #6
  7. On 11/8/2010 8:53 AM, rickman wrote:

    > I'm not sure what your point is. Are you saying that you don't make
    > use of the built in global reset function?


    I use Altera parts, and the internal "reset" logic is fixed.
    Pins go to Z and flops go to 0.

    > Of course if you use logic to generate
    > your own system reset you can set it to whatever you want independent
    > of the configuration value.


    This is what I have have always done.
    Otherwise, the only way to force a "reset"
    is to reload the configuration.

    -- Mike Treseler
     
    Mike Treseler, Nov 9, 2010
    #7
  8. Merciadri Luca

    rickman Guest

    On Nov 9, 1:13 pm, Mike Treseler <> wrote:
    > On 11/8/2010 8:53 AM, rickman wrote:
    >
    > > I'm not sure what your point is.  Are you saying that you don't make
    > > use of the built in global reset function?

    >
    > I use Altera parts, and the internal "reset" logic is fixed.
    > Pins go to Z and flops go to 0.


    I thought they had dropped that long ago. I have used some pretty old
    Altera parts and what they do to provide a preset condition is to
    reset the FF and treat the signal as a low true. Otherwise there are
    things you couldn't do properly.


    > > Of course if you use logic to generate
    > > your own system reset you can set it to whatever you want independent
    > > of the configuration value.

    >
    > This is what I have have always done.
    > Otherwise, the only way to force a "reset"
    > is to reload the configuration.


    I am pretty sure Altera parts have the exact same functionality of a
    system reset that the Xilinx and Lattice parts do, but it has been
    years since I have used their tools. One of us needs to check the
    docs... I'll do that when I get some time.

    Rick
     
    rickman, Nov 10, 2010
    #8
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