query related to PL080 ARM DMA

Discussion in 'VHDL' started by anupam.jain21@gmail.com, Jul 19, 2006.

  1. Guest

    hi,
    The Problem is related to DMA PL080.
    It has two AHB master and one AHB slave Port. AHB slave is to program
    the DMA while the two master interfaces are used for data transfer. If
    i use one master port to fetch data from the source to the DMA fifo and
    other master port to transfer data from DMA fifo to destination.
    If Hresp=SPLIT come on one port,the transmission is supposed to stop at
    both ends.
    How will the other master be effected? Will it also relinquishes the
    bus or not?


    regards,
    Anupam Jain
    , Jul 19, 2006
    #1
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