ram model

Discussion in 'VHDL' started by ashutosh_k, Apr 17, 2006.

  1. ashutosh_k

    ashutosh_k Guest

    hi

    I have a text file that contains about 50,000 hex words (each 8 bits).
    now i have to read these words into a code and do some process.
    textio is not supported in vhdl..so i have to send these words to a ram
    on the target borad.(am i right?) how do i do this ...sending words
    from a text file to a ram..
    i read this on the group about ram model..can some one sujjest the
    process to do the same. some good links for this

    ashu
    ashutosh_k, Apr 17, 2006
    #1
    1. Advertising


  2. > textio is not supported in vhdl..


    Textio is supported in VHDL:

    use std.textio.all;
    Michelangelo Masini, Apr 22, 2006
    #2
    1. Advertising

  3. ashutosh_k

    Andy Guest

    If you only need to initialize the ram (in simulation), then you can
    write a function that uses text-io to compute the initial contents,
    then returns the array data. Then call that function when you
    declare/initialize the array:

    signal ram : my_array := init_array(file);

    Andy
    Andy, Apr 24, 2006
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Robert Posey
    Replies:
    0
    Views:
    665
    Robert Posey
    Nov 26, 2003
  2. Hongtu
    Replies:
    3
    Views:
    1,005
    Hongtu
    Oct 8, 2004
  3. ashu
    Replies:
    1
    Views:
    446
  4. ashu
    Replies:
    2
    Views:
    599
    mysticlol
    Nov 6, 2006
  5. Xin Xiao

    Block RAM Distributed RAM

    Xin Xiao, Jan 7, 2008, in forum: VHDL
    Replies:
    8
    Views:
    1,443
    Duane Clark
    Jan 7, 2008
Loading...

Share This Page