Reading internal signals through a testbench.

Discussion in 'VHDL' started by CODE_IS_BAD, Sep 5, 2005.

  1. CODE_IS_BAD

    CODE_IS_BAD Guest

    Hi all,
    Through a testbench (Verilog or VHDL), how do I read the values of
    signals of a sub module through a top module? This is required to match
    and assert if the program is working correctly. Please help. Thank you.

    Best Regards,
     
    CODE_IS_BAD, Sep 5, 2005
    #1
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  2. Mike Treseler, Sep 5, 2005
    #2
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  3. CODE_IS_BAD

    Guest


    > Through a testbench (Verilog or VHDL), how do I read the values of
    > signals of a sub module through a top module?

    Use the 'signal spy' feature of ModelSim (but before that, check if
    your version of ModelSim supports it or not).
     
    , Sep 6, 2005
    #3
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