Can we log internal signals from a testbench in VHDL?

Discussion in 'VHDL' started by py, Nov 9, 2012.

  1. py

    py Guest

    Hi,

    At the end of a test, I would like to collect some stat in the following manner:

    assert false report "Max counter is " & str(counter_value) severity note

    This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer? I heard that for verilog, it is possible to reference internal signal like outer_layer.inner_layer.signal_name


    Thanks
    py, Nov 9, 2012
    #1
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  2. Hi py!

    > This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer?


    Declare a signal in a package - a "global" signal. Write to this signal
    inside your subcomponent, read this signal wherever you want. All you
    need is to include this package in all components where you read/write
    this signal.

    To make this subcomponent synthesizeable use
    -- pragma translate_off
    .... your problemativ VHDL code here ...
    -- pragma translate_off

    As an alternative you can use a "shared variable". This can be written
    from several locations while the signal should be written only from one
    location.

    Ralf
    Ralf Hildebrandt, Nov 9, 2012
    #2
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  3. py

    py Guest

    On Thursday, November 8, 2012 11:23:29 PM UTC-8, Ralf Hildebrandt wrote:
    > Hi py!
    >
    >
    >
    > > This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer?

    >
    >
    >
    > Declare a signal in a package - a "global" signal. Write to this signal
    >
    > inside your subcomponent, read this signal wherever you want. All you
    >
    > need is to include this package in all components where you read/write
    >
    > this signal.
    >
    >
    >
    > To make this subcomponent synthesizeable use
    >
    > -- pragma translate_off
    >
    > ... your problemativ VHDL code here ...
    >
    > -- pragma translate_off
    >
    >
    >
    > As an alternative you can use a "shared variable". This can be written
    >
    > from several locations while the signal should be written only from one
    >
    > location.
    >
    >
    >
    > Ralf


    Wow that's fast, thanks!
    py, Nov 9, 2012
    #3
  4. py

    Sean Durkin Guest

    Hi,

    py wrote:
    > Hi,
    >
    > At the end of a test, I would like to collect some stat in the
    > following manner:
    >
    > assert false report "Max counter is " & str(counter_value) severity
    > note
    >
    > This syntax won't work if counter_value is embedded inside DUT and is
    > not a IO port. Is there any way to "peak" inside the inner layer? I
    > heard that for verilog, it is possible to reference internal signal
    > like outer_layer.inner_layer.signal_name


    if you use Modelsim, there's the "modelsim_util" package with functions
    for that purpose. You can use it like this:

    library modelsim_lib;
    use modelsim_lib.util.all;

    -- entity, architecture, signal declarations skipped

    -----------------------------------------------------------------------------
    -- spy process
    -----------------------------------------------------------------------------
    sig_spy : process is
    begin
    init_signal_spy("/DUT/submodule1/submodule2/interesting_sig",
    "tb_sig", 1);
    wait;
    end process sig_spy;

    Here, you connect a signal from somewhere inside your DUT to another
    signal in your test bench and can then use it there for whatever you need.

    Also, in VHDL2008 hierarchical references are supported, so you can do
    stuff like this (taken from the Modelsim documentation):

    REPORT "Test Pin = " & integer'image(<<SIGNAL .tb.dut.i0.tp : natural>>)
    SEVERITY note;

    The test bench has to be compiled as VHDL2008, obviously (by calling the
    compiler with a corresponding option).

    This is part of the VHDL2008 standard, so should work with every
    simulator that supports it. But at the moment not every tool vendor has
    implemented all of VHDL2008, so this specific feature might not be
    supported by your simulator.

    Greetings,
    Sean
    Sean Durkin, Nov 9, 2012
    #4
  5. py

    py Guest

    Hi Sean,

    I tried the hierachical referenece method and ran into an issue. It does work if I could reference a signal in an instantiated module. However, what should the syntax be if a module is generated? ie:

    gen_counter : for idx in 0 to max-1 generate

    counter: entity work.counter
    ....
    ....

    end generate gen_counter;

    The signal I want to reference inside the counter module.


    Thank you


    On Friday, 9 November 2012 00:25:30 UTC-8, Sean Durkin wrote:
    > Hi, py wrote: > Hi, > > At the end of a test, I would like to collect some stat in the > following manner: > > assert false report "Max counter is "& str(counter_value) severity > note > > This syntax won't work if counter_value is embedded inside DUT and is > not a IO port. Is there any way to "peak" inside the inner layer? I > heard that for verilog, it is possible toreference internal signal > like outer_layer.inner_layer.signal_name if you use Modelsim, there's the "modelsim_util" package with functions for thatpurpose. You can use it like this: library modelsim_lib; use modelsim_lib.util.all; -- entity, architecture, signal declarations skipped ----------------------------------------------------------------------------- -- spy process ----------------------------------------------------------------------------- sig_spy : process is begin init_signal_spy("/DUT/submodule1/submodule2/interesting_sig", "tb_sig", 1); wait; end process sig_spy; Here, you connect a signal from somewhere inside your DUT to another signal in your test bench and can then use it there for whatever you need. Also, in VHDL2008hierarchical references are supported, so you can do stuff like this (taken from the Modelsim documentation): REPORT "Test Pin = " & integer'image(<<SIGNAL .tb.dut.i0.tp : natural>>) SEVERITY note; The test bench has to becompiled as VHDL2008, obviously (by calling the compiler with a corresponding option). This is part of the VHDL2008 standard, so should work with every simulator that supports it. But at the moment not every tool vendor has implemented all of VHDL2008, so this specific feature might not be supported by your simulator. Greetings, Sean
    py, Nov 9, 2012
    #5
  6. py

    Andy Guest

    Each counter label will have the generate index appended to it. You should be able to see this in the name of the signal if you trace it.

    Andy
    Andy, Nov 12, 2012
    #6
  7. py

    Sean Durkin Guest

    py wrote:
    > Hi Sean,
    >
    > I tried the hierachical referenece method and ran into an issue. It
    > does work if I could reference a signal in an instantiated module.
    > However, what should the syntax be if a module is generated? ie:
    >
    > gen_counter : for idx in 0 to max-1 generate
    >
    > counter: entity work.counter ... ...
    >
    > end generate gen_counter;
    >
    > The signal I want to reference inside the counter module.


    Yeah, I'm always unclear about that, too. :)

    Usually I just click through the hierarchy in the simulator GUI and then
    copy&paste the displayed hierarchy name.

    HTH,
    Sean
    Sean Durkin, Nov 13, 2012
    #7
  8. py

    py Guest

    Sorry guys, still can't get this to work :(

    TB code:
    assert(false) report "Maximum FIFO depth: " & to_string(<<signal .tb.dut.gen_module__0.module.fifo_depth : std_logic_vector>>) severity note;

    Copy and Paste from sim environment
    sim:/tb/dut/gen_module__0/module/fifo_depth

    For some reason, I would get the following compile error from Riviera Pro:

    COMP96 ERROR COMP96_0010: "Invalid literal." "../tb.vhd" 675 98
    COMP96 ERROR COMP96_0018: "Identifier expected expected." "../tb.vhd" 675 98

    The 98th character position is right at the beginning of 'gen_module__0', so it looks like from the compiler's POV, the module is not yet generated.

    Note that if I have something other than gen_module__0 in place, then the code would actually compiled, but would then fail at elaboration. So I do think we are moving at the right direction.



    On Tuesday, 13 November 2012 03:00:53 UTC-8, Sean Durkin wrote:
    > py wrote:
    >
    > > Hi Sean,

    >
    > >

    >
    > > I tried the hierachical referenece method and ran into an issue. It

    >
    > > does work if I could reference a signal in an instantiated module.

    >
    > > However, what should the syntax be if a module is generated? ie:

    >
    > >

    >
    > > gen_counter : for idx in 0 to max-1 generate

    >
    > >

    >
    > > counter: entity work.counter ... ...

    >
    > >

    >
    > > end generate gen_counter;

    >
    > >

    >
    > > The signal I want to reference inside the counter module.

    >
    >
    >
    > Yeah, I'm always unclear about that, too. :)
    >
    >
    >
    > Usually I just click through the hierarchy in the simulator GUI and then
    >
    > copy&paste the displayed hierarchy name.
    >
    >
    >
    > HTH,
    >
    > Sean
    py, Nov 13, 2012
    #8
  9. py

    Sean Durkin Guest

    Hi,

    py wrote:
    > Sorry guys, still can't get this to work :(
    >
    > TB code: assert(false) report "Maximum FIFO depth: " &
    > to_string(<<signal .tb.dut.gen_module__0.module.fifo_depth :
    > std_logic_vector>>) severity note;
    >
    > Copy and Paste from sim environment
    > sim:/tb/dut/gen_module__0/module/fifo_depth
    >
    > For some reason, I would get the following compile error from Riviera
    > Pro:
    >
    > COMP96 ERROR COMP96_0010: "Invalid literal." "../tb.vhd" 675 98
    > COMP96 ERROR COMP96_0018: "Identifier expected expected." "../tb.vhd"
    > 675 98
    >
    > The 98th character position is right at the beginning of
    > 'gen_module__0', so it looks like from the compiler's POV, the module
    > is not yet generated.
    >
    > Note that if I have something other than gen_module__0 in place, then
    > the code would actually compiled, but would then fail at elaboration.
    > So I do think we are moving at the right direction.


    hmm, can't help you on that one, I'm afraid. I guess we need one of the
    VHDL gurus now... :)

    Is "fifo_depth" an unconstrained std_logic_vector? If not, maybe you
    need to specify the actual range for it so the tool can find it. Just
    guessing...

    Bye,
    Sean
    Sean Durkin, Nov 14, 2012
    #9
  10. py

    py Guest

    On Wednesday, 14 November 2012 04:56:16 UTC-8, Sean Durkin wrote:
    > Hi, py wrote: > Sorry guys, still can't get this to work :( > > TB code: assert(false) report "Maximum FIFO depth: " & > to_string(<<signal .tb.dut.gen_module__0.module.fifo_depth : > std_logic_vector>>) severity note; > > Copy and Paste from sim environment > sim:/tb/dut/gen_module__0/module/fifo_depth > > For some reason, I would get the following compile error from Riviera > Pro: > > COMP96 ERROR COMP96_0010: "Invalid literal." "../tb.vhd" 675 98 > COMP96 ERROR COMP96_0018: "Identifier expected expected." "../tb.vhd" > 675 98 > > The 98th character position is right at the beginning of > 'gen_module__0', so it looks like from the compiler's POV, the module > is not yet generated. > > Note that if I have something other than gen_module__0 in place, then > the code would actually compiled, but would then fail at elaboration. > So I do think we are moving at the right direction. hmm, can't help you on that one, I'm afraid. I guess we need one of the VHDL gurus now... :) Is "fifo_depth" an unconstrained std_logic_vector? If not, maybe you need to specify the actual range for it so the tool can find it. Justguessing... Bye, Sean



    fifo_depth has a fixed range
    signal fifo_depth : std_logic_vector(8 downto 0);

    Thanks for your time, we are getting there :)
    py, Nov 15, 2012
    #10
  11. py

    py Guest

    Hi,

    Thanks for the tip. I certainly had tried the LRM naming convention you suggest, and in return, I would see the following Riviera elaboration error:

    # ELBREAD: Elaboration time 5.4 .
    # KERNEL: Main thread initiated.
    # KERNEL: Kernel process initialization phase.
    # KERNEL: Time resolution set to 1ps.
    # ELAB2: Elaboration final pass...
    # KERNEL: PLI/VHPI kernel's engine initialization done.
    # PLI: Loading library '/usr/local/riviera-pro-2012.02-x86_64/bin/libsystf.so'
    # VHPI: Loading library 'systf.so'
    # ELAB2: Create instances ...
    # ELAB2: Fatal Error: ELAB2_0135 tb.vhd (519): Subtype indication of external name that denotes an unelaborated object is not fully constrained or external name does not exist.
    # KERNEL: Error: E8005 : Kernel process initialization failed.
    # VSIM: Error: Simulation initialization failed.

    The total number of instances generated in the generate statement is set to a constant (and I also tried just force it to a number), so I'm guessing it's not about instances being fully constraint?


    Thanks

    > The name "py" posted isn't following the LRM. The LRM says the names
    >
    > will be generated with parantheses e.g.
    >
    >
    >
    > gen_module(0).module
    >
    >
    >
    > I know that Modelsim changed the way they displayed names in the
    >
    > hierarchy viewer in a recent version to follow the LRM properly,
    >
    >
    >
    > regards
    >
    > Alan
    >
    >
    >
    > --
    >
    > Alan Fitch
    py, Nov 20, 2012
    #11
  12. py

    py Guest

    Hi,

    Sorry, was busy this week so this reply comes a bit late. The code I tried is

    assert(false) report "Maximum FIFO depth: " & to_string(<<signal .tb.dut.gen_sample_reader__0.sample_reader.request_fifo_depth_wr_max : std_logic_vector>>) severity note;
    -> fails during compile

    assert(false) report "Maximum FIFO depth: " & to_string(<<signal .tb.dut.gen_sample_reader(0).sample_reader.request_fifo_depth_wr_max : std_logic_vector>>) severity note;
    -> fails during elaboration

    instance_name looks like it could be useful. Is there any quick way to convert the output to a string so that I can display it?

    assert(i_req = '0') report "DEBUG: " & to_string(req_fifo_depth_wr_max'instance_name);

    VHDL2008 was enabled via the -hdl_version 2008 compile flag.


    Thanks!


    On Wednesday, 21 November 2012 16:20:01 UTC-8, Alan Fitch wrote:
    > On 20/11/12 22:42, py wrote:
    >
    > > Hi,

    >
    > >

    >
    > > Thanks for the tip. I certainly had tried the LRM naming convention you suggest, and in return, I would see the following Riviera elaboration error:

    >
    > >

    >
    > > # ELBREAD: Elaboration time 5.4 .

    >
    > > # KERNEL: Main thread initiated.

    >
    > > # KERNEL: Kernel process initialization phase.

    >
    > > # KERNEL: Time resolution set to 1ps.

    >
    > > # ELAB2: Elaboration final pass...

    >
    > > # KERNEL: PLI/VHPI kernel's engine initialization done.

    >
    > > # PLI: Loading library '/usr/local/riviera-pro-2012.02-x86_64/bin/libsystf.so'

    >
    > > # VHPI: Loading library 'systf.so'

    >
    > > # ELAB2: Create instances ...

    >
    > > # ELAB2: Fatal Error: ELAB2_0135 tb.vhd (519): Subtype indication of external name that denotes an unelaborated object is not fully constrained or external name does not exist.

    >
    > > # KERNEL: Error: E8005 : Kernel process initialization failed.

    >
    > > # VSIM: Error: Simulation initialization failed.

    >
    > >

    >
    > > The total number of instances generated in the generate statement is set to a constant (and I also tried just force it to a number), so I'm guessing it's not about instances being fully constraint?

    >
    > >

    >
    > Oh.
    >
    >
    >
    > Can you post the exact path you typed in to the code?
    >
    >
    >
    > Also have you tried using 'instance_name to print out the path?
    >
    >
    >
    > Finally (probably a stupid question) have you enabled VHDL-2008 when
    >
    > compiling?
    >
    >
    >
    > regards
    >
    > Alan
    >
    >
    >
    >
    >
    > --
    >
    > Alan Fitch
    py, Nov 30, 2012
    #12
  13. py <> writes:

    > instance_name looks like it could be useful. Is there any quick way to convert
    > the output to a string so that I can display it?
    >
    > assert(i_req = '0') report "DEBUG: " &
    > to_string(req_fifo_depth_wr_max'instance_name);
    >


    I may be missing something, but isn't the instance_name property already
    a string?

    assert(i_req = '0') report "DEBUG: " & req_fifo_depth_wr_max'instance_name;

    should be fine.

    --

    TRW Conekt - Consultancy in Engineering, Knowledge and Technology
    http://www.conekt.co.uk/capabilities/39-electronic-hardware
    Martin Thompson, Nov 30, 2012
    #13
  14. py

    py Guest

    Opps, you are right! Here is the output on the console

    tb(struct):dut@module(rtl):gen_sample_reader(0):sample_reader@module(rtl):req_fifo_depth_wr_max

    so according to this, this should had work right? But Riviera elaboration process complained about it. I guess it is time to email support.

    .tb.dut.gen_sample_reader(0).sample_reader.request_fifo_depth_wr_max


    On Friday, 30 November 2012 01:49:12 UTC-8, Martin Thompson wrote:
    > py <> writes:
    >
    >
    >
    > > instance_name looks like it could be useful. Is there any quick way to convert

    >
    > > the output to a string so that I can display it?

    >
    > >

    >
    > > assert(i_req = '0') report "DEBUG: " &

    >
    > > to_string(req_fifo_depth_wr_max'instance_name);

    >
    > >

    >
    >
    >
    > I may be missing something, but isn't the instance_name property already
    >
    > a string?
    >
    >
    >
    > assert(i_req = '0') report "DEBUG: " & req_fifo_depth_wr_max'instance_name;
    >
    >
    >
    > should be fine.
    >
    >
    >
    > --
    >
    >
    >
    > TRW Conekt - Consultancy in Engineering, Knowledge and Technology
    >
    > http://www.conekt.co.uk/capabilities/39-electronic-hardware
    py, Dec 1, 2012
    #14
  15. py

    Jim Lewis Guest

    With external names, instance order is important. Make sure to instance the DUT before other testbench code. This will make sure the DUT has been elaborated before you try to access the signal. Aliases in the architecture will be problematic for this same reason.

    Good luck,
    Jim
    Jim Lewis, Dec 5, 2012
    #15
  16. py

    py Guest

    Sorry for the late update. I ended up contacting Riviera on this issue and it looks like the culprit is a compiler bug. The correct format was shown by the simulator all along

    Cheers,
    py, Feb 20, 2013
    #16
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