shared buses in Max Plus

Discussion in 'VHDL' started by Jluis, Apr 17, 2004.

  1. Jluis

    Jluis Guest

    Hi everyone!!!

    I´m implementing a PROCESSOR in VHDL, but I have a problem when I try
    to connect the componets in my top file. The problem is when I assign
    many sources at one signal(on the Port Map), i.e. My signals are
    conected at one bus. like this::

    U1: instreg PORT MAP( opcode => opcode,datain => bus, DIRout => buss,
    Kout => buss, dataout => buss, etc.....);

    U2: proc PORT MAP(datain => buss, dataout => buss, etc....);

    I also read that I can implement a Resolution Functions to solve this
    problem, but You know, the resolution function is not supported for
    Max-Plus II. ....

    does everybody know how I can solve this problem or know other way to
    implement it?

    I used MaxPlus and FPGA from ALTERA,
    thanks in advance
    best regards

    JLuis
    MÉXICO
     
    Jluis, Apr 17, 2004
    #1
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  2. Jluis wrote:

    > I´m implementing a PROCESSOR in VHDL, but I have a problem when I try
    > to connect the componets in my top file. The problem is when I assign
    > many sources at one signal(on the Port Map), i.e. My signals are
    > conected at one bus. like this::
    >
    > U1: instreg PORT MAP( opcode => opcode,datain => bus, DIRout => buss,
    > Kout => buss, dataout => buss, etc.....);
    >
    > U2: proc PORT MAP(datain => buss, dataout => buss, etc....);


    What do you expect, if DIRout of instreg drives '0' and dataout of proc
    drives '1' to signal buss?
    This is not allowed.

    There two common ways to solve it:

    * classic mux: Depending on an additional signal (often an address) the
    mux takes one signal and muxes it to the bus.

    * tri-state mux: Depending on additional signals, one and only one
    component drives to the bus. All others drive 'Z'.


    > I also read that I can implement a Resolution Functions to solve this
    > problem,


    std_logic(_vector) is a resolved signal, that allows you to use
    tri-state muxes.


    > but You know, the resolution function is not supported for
    > Max-Plus II. ....


    No tri-state muxes allowed? -> Take classic muxes.

    Ralf
     
    Ralf Hildebrandt, Apr 18, 2004
    #2
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  3. Jluis

    Jluis Guest

    Thanks I solved the problem, I put a process inside of my top level....
    JLuis


    Ralf Hildebrandt <> wrote in message news:<c5toce$5gv25$-berlin.de>...
    > Jluis wrote:
    >
    > > I´m implementing a PROCESSOR in VHDL, but I have a problem when I try
    > > to connect the componets in my top file. The problem is when I assign
    > > many sources at one signal(on the Port Map), i.e. My signals are
    > > conected at one bus. like this::
    > >
    > > U1: instreg PORT MAP( opcode => opcode,datain => bus, DIRout => buss,
    > > Kout => buss, dataout => buss, etc.....);
    > >
    > > U2: proc PORT MAP(datain => buss, dataout => buss, etc....);

    >
    > What do you expect, if DIRout of instreg drives '0' and dataout of proc
    > drives '1' to signal buss?
    > This is not allowed.
    >
    > There two common ways to solve it:
    >
    > * classic mux: Depending on an additional signal (often an address) the
    > mux takes one signal and muxes it to the bus.
    >
    > * tri-state mux: Depending on additional signals, one and only one
    > component drives to the bus. All others drive 'Z'.
    >
    >
    > > I also read that I can implement a Resolution Functions to solve this
    > > problem,

    >
    > std_logic(_vector) is a resolved signal, that allows you to use
    > tri-state muxes.
    >
    >
    > > but You know, the resolution function is not supported for
    > > Max-Plus II. ....

    >
    > No tri-state muxes allowed? -> Take classic muxes.
    >
    > Ralf
     
    Jluis, Apr 28, 2004
    #3
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