Synopsys clock edge question

Discussion in 'VHDL' started by blarg, Jun 27, 2005.

  1. blarg

    blarg Guest

    I am having an issue with synthesizing the code below using Synopsys
    design analyzer.

    ---
    clkproc_12: process(clk)
    begin

    for index in 0 to num_stg12_sad_regs-1 loop
    if (rising_edge(clk)) then
    if (rst = '1' or stg12_rst(index) = '1') then
    stg12_sad_reg((index+1)*out_size-1 downto
    index*out_size) <= "000000000000";
    elsif ((en and stg12_en(index)) = '1') then
    stg12_sad_reg((index+1)*out_size-1 downto index*out_size) <=
    stg1_add_out;
    end if;
    end if;
    end loop;

    end process;
    --

    The error that I get is:

    Error: This use of clock edge specification not supported in routine PE
    line 219 in file 'xxx/pe.vhd' (HDL-109)

    Line 219 is the "rising_edge" line. I am not sure what is wrong with
    this clock specification, is it because of it being nested in a for
    loop?

    Any help would be appreciated.
     
    blarg, Jun 27, 2005
    #1
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  2. blarg wrote:
    > I am having an issue with synthesizing the code below using Synopsys
    > design analyzer.
    >
    > ---
    > clkproc_12: process(clk)
    > begin
    >
    > for index in 0 to num_stg12_sad_regs-1 loop
    > if (rising_edge(clk)) then


    Whoops - what is this?

    You can eighter
    * have an outside for-generate statement having inside a process, to infer a
    number of similar ressources (described by the process)
    XOR
    * have a process beeing edge-sensitve and inside the edge-sensitve if-clause a for-loop
    doing some stuff

    In other words: Edge-sensitive statements are not allowed inside a for-loop by your
    synthesis tool - and I guess by any other synthesis tool.


    Ralf
     
    Ralf Hildebrandt, Jun 27, 2005
    #2
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  3. blarg

    blarg Guest

    Thanks, Ralf. for-generate worked.
     
    blarg, Jun 27, 2005
    #3
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