Use BRam and DRam on FPGA's Xilinx

Discussion in 'VHDL' started by Gordon Freeman, Apr 16, 2007.

  1. Hi everybody!
    When I write verilog code to generate RAM or ROM, the source code only
    use slices resources. But I want to use BRam or DRam resources on FPGA
    (FPGA's Xilinx) to generate RAM or ROM. Can you help me?
    Gordon Freeman, Apr 16, 2007
    #1
    1. Advertising

  2. Gordon Freeman

    Andy Guest

    The most common reason people get flops/gates when the wanted RAM is
    that they are reading/writing more than one (single port) or two (dual
    port) elements of the same array in the same clock cycle.

    Review your code to ensure this is not happening.

    Andy

    On Apr 15, 9:27 pm, "Gordon Freeman" <>
    wrote:
    > Hi everybody!
    > When I write verilog code to generate RAM or ROM, the source code only
    > use slices resources. But I want to use BRam or DRam resources on FPGA
    > (FPGA's Xilinx) to generate RAM or ROM. Can you help me?
    Andy, Apr 16, 2007
    #2
    1. Advertising

  3. Gordon Freeman

    martin.wahlstedt

    Joined:
    Mar 29, 2007
    Messages:
    14
    google xst.pdf and read the pages about memories, p. 120 ->

    Martin
    martin.wahlstedt, Apr 16, 2007
    #3
  4. Gordon Freeman

    Andy Peters Guest

    On Apr 15, 7:27 pm, "Gordon Freeman" <>
    wrote:
    > Hi everybody!
    > When I write verilog code to generate RAM or ROM, the source code only
    > use slices resources. But I want to use BRam or DRam resources on FPGA
    > (FPGA's Xilinx) to generate RAM or ROM. Can you help me?


    Depending on the FPGA family, you need to describe a synchronous read
    in order to infer a BRAM.

    -a
    Andy Peters, Apr 17, 2007
    #4
  5. Hi!

    Take a look at the XST manual (xst.pdf), chapter 2: HDL Coding
    techniques. This chapter describes detailed which HDL constructs will
    result in the usage of which FPGA resource.

    Matthias


    Gordon Freeman schrieb:
    > Hi everybody!
    > When I write verilog code to generate RAM or ROM, the source code only
    > use slices resources. But I want to use BRam or DRam resources on FPGA
    > (FPGA's Xilinx) to generate RAM or ROM. Can you help me?
    >
    Matthias Alles, Apr 18, 2007
    #5
  6. On Apr 18, 4:47 pm, Matthias Alles <-
    kl.de> wrote:
    > Hi!
    >
    > Take a look at the XST manual (xst.pdf), chapter 2: HDL Coding
    > techniques. This chapter describes detailed which HDL constructs will
    > result in the usage of which FPGA resource.
    >
    > Matthias
    >
    > Gordon Freeman schrieb:
    >
    > > Hi everybody!
    > > When I write verilog code to generate RAM or ROM, the source code only
    > > use slices resources. But I want to use BRam or DRam resources on FPGA
    > > (FPGA's Xilinx) to generate RAM or ROM. Can you help me?


    Thank you.
    Right now, I can make it.
    Gordon Freeman, Apr 23, 2007
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Brad Smallridge

    Xilinx BRAM Init VHDL formats

    Brad Smallridge, Jan 14, 2005, in forum: VHDL
    Replies:
    1
    Views:
    2,077
    Weng Tianxiang
    Jan 17, 2005
  2. Brad Smallridge

    Xilinx V-4 BRAM

    Brad Smallridge, Jan 20, 2006, in forum: VHDL
    Replies:
    0
    Views:
    3,192
    Brad Smallridge
    Jan 20, 2006
  3. Brad Smallridge

    Xilinx BRAM initialization

    Brad Smallridge, Jul 15, 2006, in forum: VHDL
    Replies:
    5
    Views:
    6,291
  4. steve

    xilinx bram not connected?

    steve, Jul 19, 2009, in forum: VHDL
    Replies:
    1
    Views:
    1,000
    steve
    Jul 20, 2009
  5. aziz
    Replies:
    0
    Views:
    1,931
Loading...

Share This Page