Use BRam and DRam on FPGA's Xilinx

[Gordon Freeman]

Hi everybody!
When I write verilog code to generate RAM or ROM, the source code only
use slices resources. But I want to use BRam or DRam resources on FPGA
(FPGA's Xilinx) to generate RAM or ROM. Can you help me?

 

[Andy]

The most common reason people get flops/gates when the wanted RAM is
that they are reading/writing more than one (single port) or two (dual
port) elements of the same array in the same clock cycle.

Review your code to ensure this is not happening.

Andy

 

[martin.wahlstedt]

google xst.pdf and read the pages about memories, p. 120 ->

Martin

 

[Andy Peters]

Hi everybody!
When I write verilog code to generate RAM or ROM, the source code only
use slices resources. But I want to use BRam or DRam resources on FPGA
(FPGA's Xilinx) to generate RAM or ROM. Can you help me?

Depending on the FPGA family, you need to describe a synchronous read
in order to infer a BRAM.

-a

 

[Matthias Alles]

Hi!

Take a look at the XST manual (xst.pdf), chapter 2: HDL Coding
techniques. This chapter describes detailed which HDL constructs will
result in the usage of which FPGA resource.

Matthias

 

[Gordon Freeman]

Hi!

Take a look at the XST manual (xst.pdf), chapter 2: HDL Coding
techniques. This chapter describes detailed which HDL constructs will
result in the usage of which FPGA resource.

Matthias

Thank you.
Right now, I can make it.