verification language

[learn_verilog]

Hello All,

I thought of learning some verification language and sole purpose is
to find a job in verification area.
I have a decent knowledge in verilog and have done several projects
in the same.
Considering my background which verification language is easy to
learn; systemverilog, systemc, vera, e.
Which particular language is preferred in Industry.......i mean in
high demand.


Regards,
learn_verilog

 

[channakeshava]

verification language in VHDL

Hi frend

Do you know any verification language in VHDL