VHDL description of an array structure

[panthera]

Hi,

I'm writing VHDL code to describe a system of which the structure is an
array of some building blocks.The inputs and outputs of such a building
block may be about 10 bits wide.And there will be around 100 of these
building blocks in the structure.So is there a smart way to do this
instead of instantiating every one of them and porting map them
together?coz otherwise it'll be a lot of copy-paste and quite
error-prone.

panthera

 

[Mike Treseler]

Hi,

I'm writing VHDL code to describe a system of which the structure is an
array of some building blocks.The inputs and outputs of such a building
block may be about 10 bits wide.And there will be around 100 of these
building blocks in the structure.So is there a smart way to do this
instead of instantiating every one of them and porting map them
together?coz otherwise it'll be a lot of copy-paste and quite
error-prone.

Consider declaring an array type of 100 10-bit vectors
in a synchronous process. Then declare a variable
of this type and write procedures to initialize
and to update this variable. A procedures
for an output port interface are needed as well.
Good luck.

-- Mike Treseler