View instantiated RAM by address in sim

[dwerdna]

Hi all

I know of a couple of ways to do this, just after other opinions..

I've instantiated some RAM16X1S RAMin a generate statement, to make a 8
bit wide RAM. When simulating I cannot see what the contents of the
RAM's memory is, because Modelsim instantiates the components
seperately, and of course each component has 1 bit per addr...

Now I could spend some time in adding in what I want to see to my
wave.do - which I have done before, and its pretty user intensive, or I
could write a TCL script to do this - which I plan to do this time. Is
there another option?? I could also have a generate statement or the
like in my actual VHDL which maps out some signals which would only be
used in simulation, except I dont believe that I can get access to the
'mem' signal inside the instantiation..


Any ideas??

Thanks

Andrew

 

[info_]

Hi Andrew,

I'm sure you _must_ have good reasons to manually instanciate
small Ram primitives & assemble them into a bigger Ram,
but usually, I try to avoid doing this.

Alternatives would be :

- instanciating a bigger Ram or a CoreGen'd or Memgen'd macro,
with the advantage of a behavioral (higher level) model with
faster simulation & a nice single array as memory contents,
ability to put breakpoints etc...

- Inference as modern synthesizers can do, with an even more
straightforward simulation path (no model library).

- If you don't want to do without instanciating small Rams,
then why not "wrap them" in a module (entity) and create
a functionally equivalent (behavioral) model ?

Tcl sure could do the fishing & reassembling, but I think
it's a lot of pain just for viewing a memory.

Treb

 

[dwerdna]

Hi Treb, Ok thanks for that. No I didnt have a good reason to manually
instanciate small RAM's, just from examples that I have seen of other
peoples code in companies that I have worked in, I thought it was the
'done' thing.. All xilinx primitives are 1 bit wide are they not, so
your suggestion of instantiating a bigger RAM would be a 3rd party
one??

Thanks

Andrew

 

[KCL]

just an example of RAM block declaration, you could do different stuff as
dual port ram here it's only a single one...

alexis


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.NUMERIC_STD.all;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity block_RAM is
Port ( clk : in std_logic;
we: in std_logic;
adress_in : in std_logic_vector (2 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end block_RAM;

architecture Behavioral of block_RAM is

signal adress_reg: std_logic_vector(2 downto 0);
signal we_reg : std_logic;
signal data_in_reg : std_logic_vector(7 downto 0);
signal data_out_reg : std_logic_vector(7 downto 0);

type TYPE_RAM is array (8 downto 0) of
std_logic_vector(7 downto 0);
----------------------------------------------------

signal memory : TYPE_RAM ;

-------------------------------------------------------
begin
process(clk)
begin
if rising_edge(clk) then
adress_reg <= adress_in;
data_in_reg <= data_in;
we_reg <= we;
if we_reg='1' then
memory( to_integer( unsigned(adress_reg))) <= data_in_reg;
else
data_out_reg <= memory( to_integer( unsigned(adress_reg))) ;
end if;
data_out <= data_out_reg;

end if;
end process;

end ;

 

[dwerdna]

Hi KCL

Following Treb's advice I just made up a quick process with some
vectors to simulate the contents of the RAM. Because I only needed a
small amount of RAM (8 wide, 16 deep) I didnt want to use up a whole
blockRAM.

Thanks

Andrew

 

[dwerdna]

Hi KCL

Sorry, I didnt look at your example all that closely, and i see that
you have suggested something similar to what I have done - and not
actaully used a BRAM which is what I initially thought you were
suggesting..

Andrew

 

[KCL]

That not use a BRAM?? ,

Is there a reset in your process??

You could look in your synthetyze option too , there is an option to infer
BRAM or distribued RAM

Alexis

 

[dwerdna]

Hi KCL

Looks like I didnt read you example all that closely yesterday - I was
in a rush to go to a meeting.. Anyway yes it looks like I have
implemented something close to what you were suggesting as a
behavourable model and it makes life alot easier

Thanks

Andrew

 

[dwerdna]

Yes I see that its not a BRAM, which was the mistake I initally made
when looking at your example.

My behavourable process works fine for what i need, and the system
writes into the whole RAM after reset, so there is no problems there
with unknown values etc

Yes I want to use distributed RAM, therefore I was instantiating that
type of xilinx primitive. I will look into making sure that they dont
get synthesised into BRAM, though if there is BRAM to spare then it
doesnt matter i guess. I just didnt want to use up a whole BRAM when I
may like to use it for something needing more space somewhere else in
my system

Thanks

Andrew