Wait statement error

[Shannon]

I'm starting to use ModelSim (the version included with Quartus II)
for my simulations. I've been a long time user of the waveform
simulator in Quartus but I thought I should stop using stone-knives
and bear-skins.

One problem I've hit early on: I have the following process in my
testbench:

DACclock : PROCESS
BEGIN
wait for 4 ns; DAC_clk <= not DAC_clk;
end PROCESS DACclock;

Seems pretty straightforward eh? ModelSim likes it and produces the
clock waveform that I would expect. Quartus however complains:

Error (10533): VHDL Wait Statement error at HighSpeedDACTB.vhd(72):
Wait Statement must contain condition clause with UNTIL keyword

Huh?

Shannon

 

[Tricky]

I'm starting to use ModelSim (the version included with Quartus II)
for my simulations.  I've been a long time user of the waveform
simulator in Quartus but I thought I should stop using stone-knives
and bear-skins.

One problem I've hit early on: I have the following process in my
testbench:

DACclock : PROCESS
BEGIN
   wait for 4 ns; DAC_clk  <= not DAC_clk;
end PROCESS DACclock;

Seems pretty straightforward eh?  ModelSim likes it and produces the
clock waveform that I would expect.  Quartus however complains:

Error (10533): VHDL Wait Statement error at HighSpeedDACTB.vhd(72):
Wait Statement must contain condition clause with UNTIL keyword

Huh?

Shannon

Id raise it as an Issue with Altera, but given that they include
Modelsim AE, they'll probably just tell you to use that instead.

 

[JimLewis]

Shannon
Is this from the Quartus synthesis tool? You only need to
tell the synthesis tool about your design. There may be a
place to mark the file as a testbench file - make sure to
do this as synthesis tools don't like many things that are
part of the testbench.

Cheers,
Jim
SynthWorks VHDL Training

 

[joris]

You may need to place the testbench in a seperate file (just guessing it might be an issue here as well, this seems the case with the Xilinx tool anyway)

 

[Shannon]

Shannon
Is this from the Quartus synthesis tool?  You only need to
tell the synthesis tool about your design.  There may be a
place to mark the file as a testbench file - make sure to
do this as synthesis tools don't like many things that are
part of the testbench.

Cheers,
Jim
SynthWorks VHDL Training

It was from the "Analysis & Elaboration" tool. But I think I get the
picture now. When I tried to archive the whole project it said that
it had to do "Analysis & Elaboration" first. I just clicked on
"yes". I don't think it understands that it is a testbench project
and Elaboration is silly. (At least I think that is what is going on.)

 

[Mike Treseler]

It was from the "Analysis & Elaboration" tool. But I think I get the
picture now. When I tried to archive the whole project it said that
it had to do "Analysis & Elaboration" first. I just clicked on
"yes". I don't think it understands that it is a testbench project
and Elaboration is silly. (At least I think that is what is going on.)

Quartus only knows about vhdl for *synthesis*.
Quartus cannot use vhdl code for simulation.
The quartus sim tool only knows about altera netlists and waveforms.
For a vhdl testbench, use modelsim.

-- Mike Treseler

 

[Shannon]

Quartus only knows about vhdl for *synthesis*.
Quartus cannot use vhdl code for simulation.
The quartus sim tool only knows about altera netlists and waveforms.
For a vhdl testbench, use modelsim.

     -- Mike Treseler

Agreed.

Next step is get get ModelSim to understand my memory initialization
file.

Shannon

 

[Shannon]

Quartus only knows about vhdl for *synthesis*.
Quartus cannot use vhdl code for simulation.
The quartus sim tool only knows about altera netlists and waveforms.
For a vhdl testbench, use modelsim.

     -- Mike Treseler

Agreed.

Next step is get get ModelSim to understand my memory initialization
file.

Shannon

 

[Mike Treseler]

Next step is get get ModelSim to understand my memory initialization
file.

I would make that a vhdl constant array.

-- Mike Treseler