helo..i m a big noob here bout vhdl..can u guys trace the problem bout a part of coding here..
proc_motor : process begin
motor <= motor_stop;
wait until rising_edge( clock );
while req_above = '1' loop
motor <= motor_up;
wait until rising_edge( clock );
if i_at_floor = '1'
and ( i_req_up( to_integer( i_cur_floor ) ) = '1'
or i_req_exit( to_integer( i_cur_floor ) ) = '1'
its error states that Process Statement must contain only one Wait Statement. :stupido:
proc_motor : process begin
motor <= motor_stop;
wait until rising_edge( clock );
while req_above = '1' loop
motor <= motor_up;
wait until rising_edge( clock );
if i_at_floor = '1'
and ( i_req_up( to_integer( i_cur_floor ) ) = '1'
or i_req_exit( to_integer( i_cur_floor ) ) = '1'
its error states that Process Statement must contain only one Wait Statement. :stupido: