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Hi people, i got a simple code for making an ADC and when i test it on behavioral simulation is all perfect, but when i test it on post route simulation.....well, it´s all WRONG. And now i want to make a "step by step view" to find the causes, like the one´s that can be possible on behavioral simulation(add breakpoints,etc), but on post route simulation i can´t see my code to put a breakpoint and now i don´t know how to do to find the causes of the wrong simulation
How do you find the "errors" on your code when (for example) you fpga is not doing what you want (remember that the behavioral simulation is correct)??
PS: I use Xilinx ISE 8.2i to write vhdl and sorry for my english
How do you find the "errors" on your code when (for example) you fpga is not doing what you want (remember that the behavioral simulation is correct)??
PS: I use Xilinx ISE 8.2i to write vhdl and sorry for my english