[ANN] LOOPGEN-Fast hardware looping VHDL IPs

Discussion in 'VHDL' started by Nikolaos Kavvadias, Jun 13, 2013.

  1. The LOOPGEN IP collection provides fast hardware architectures for
    implementing nested loop structures. The collection comprises of
    different architectures (variants), namely:
    - HWLU, a mixed-level structural/RTL architecture,
    - IXGENB, a behavioral-level and
    - IXGENR, a high-performance, pure RTL description of a more
    generalized form
    of the architecture.

    Hardware looping architectures have potential uses for data-intensive
    processing in embedded systems. The implemented architectures are able
    execute perfect loop nests without any cycle overhead for updating
    iteration vector. Actually, successive last iterations of nested loops
    collapsed in a single cycle.

    LOOPGEN can be used as a ROYALTY-FREE component for use in your

    Interesting features and characteristics of LOOPGEN include:
    - three different architectural variants
    - support for any number of loops and datapath bitwidth
    - single-cycle iteration vector update
    - 201-243 MHz achieved clock rates on Xilinx Virtex-6.

    The LOOPGEN IPs comprise of the following deliverables:
    - Documentation in ASCII text, PDF, HTML formats
    - Vendor-independent VHDL code for all architectural variants
    - Configurable testbench
    - HDL code generators for the HWLU and IXGENR architectures
    - Various helper scripts for simulation (GHDL, Modelsim) and

    All users that will register and download LOOPGEN within 2013 are
    to the following:
    - FREE updates for the entire lifetime of the product
    - FREE email support.

    Pricing information and sample downloads:

    Best regards,
    Nikolaos Kavvadias <>
    Hardware and EDA tools developer, Research Scientist
    Lamia, Fthiotis, Greece
    Nikolaos Kavvadias, Jun 13, 2013
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