[ANNOUNCE] YARDstick - custom processor development toolset

U

Uncle Noah

ANNOUNCE: YARDstick - custom processor development toolset

Dear friends,

I am very pleased and proud to announce YARDstick:
http://electronics.physics.auth.gr/people/nkavv/yardstick,
a custom processor development toolset with an impressive list of
features.

YARDstick is a novel design automation tool for custom processor
development flows
that focuces on the hard part: generating and evaluating application-
specific hardware extensions. YARDstick is a powerful building block
for ASIP development, since it integrates application analysis, ultra-
fast algorithms for custom instruction generation and selection with
user-defined compiler intermediate representations. As of September
2007, YARDstick integrates retargetable compiler features for the
targeted IRs/architectures. Remarkable features of YARDstick are the
following:

- retargetable to used-defined IRs by machine description.
- can be targeted to low-level compiler IRs, assembly-level
representations of virtual
machines, or assembly code for existing processors.
- fully parameterized custom instruction generation and selection
engine.
- lightning-fast code selector for multiple-input multiple-output
patterns based on
graph matching. It is known that the code selector scales very well
with the instruction
node count of basic block data-dependence graphs (successfully
tested with custom
instruction patterns of more than 30 nodes).
- virtual register assignment for virtual machine targets.
- an extensive set of backends including assembly code emitter, C
backend, visualization
backends for Graphviz and VCG (or aiSee), an XML format amenable to
graph rewriting
and others.

YARDstick comes along with a cross-platform GUI written in Tcl/Tk 8.5.

The ultimate goal of YARDstick is to liberate the designer's
development infrastructure
from compiler and simulator idiosyncrasies. With YARDstick, the ASIP
designer is empowered
with the freedom of specifying the target architecture of choice and
adding new implementations of analyses and custom instruction
generation/selection methods.

At this moment, YARDstick is being heavily used for developing a new
processor architecture of mine with many never-being-seen features,
mostly aiming FPGAs. Status update report on the processor
architecture should be expected near late October 2007.

Typically, 2x to 15x speedups for benchmark applications (ANSI C
optimized source code)
can be fully automatically obtained by using YARDstick depending on
the target architecture. Speedups are evaluated against a typical
scalar RISC architecture.

Detailed feature list:

1. Analysis engines generating both static and dynamic statistics:
- Data types
- Operation-level statistics
- Basic block statistics (ranking)
- Performance estimations with/without custom instructions.

2. Generation of CDFGs (Control-Data Flow Graphs).

3. Backend engines:
- ANSI C
- dot (Graphviz)
- VCG (GDL, aiSee)
- XML (GGX for the AGG graph rewriting tool)
- Retargetable assembly emitter for entire translation units
(single files with multiple functions/procedures).
- CDFG formats for various RTL synthesis tools.

4. Custom instruction engines:
- Full-parameterized MIMO custom instruction generation algorithm.
Features:
* Fast heuristic !!!
* Configurable number of inputs
* Configurable number of outputs
* List of forbidden nodes
* Node sorting strategies (3 different strategies!)
* Transformation rule library for applying CFG transformation
strategies

5. Custom instruction selection:
- Based on priority metrics (2 choices at the moment).

6. Graph (and graph-subgraph) isomorphism features for eliminating
redundant patterns. Multiple algorithms supported.

7. Visualization of custom instructions, basic blocks, control-flow
graphs and control-data flow graphs (basic block nodes expanded to
their constituent instructions).

8. Basic retargetable compiler features (alpha state):
- Code selector for MIMO instructions (tested with large cases).
- Virtual register assignment (allocation for a VM).
- Hard register allocator in the works.

9. Miscellaneous features:
- single constant multiplication optimizer
- elimination of false data-dependences in assembly-level CDFGs.
- beautification options for visualization
- interfacing (co-operation) with external tools such as peephole
optimizers, profilers, code generators etc.
- features related to the custom processor architecture (not to be
disclosed yet)

Here is a list of application benchmarks that have been tested with
YARDstick (compiler
features not fully tested):
- ADPCM encoder and decoder (typically: 4x speedup)
- Video processing kernels: full-search block-matching motion
estimation, logarithmic search motion estimation, motion compensation
- Image processing kernels: steganography (hide/uncover), edge
detection, matrix multiplication
- Cryptographic kernels: crc32, rc5, raiden (7x speedup, 12x for
unrolled version)

At the YARDstick homepage:
http://electronics.physics.auth.gr/people/nkavv/yardstick/
you can find some additional material:

- 2-page brochure
- 2-page abstract for the DATE'07 University Booth
- a more extended presentation on YARDstick

The above material refers to the status of April 2007.


Expected enhancements to YARDstick in the near future:
- linear-scan and integer-linear programming based register
allocators
- bitwidth analysis
- CDFG->VHDL generation of custom instruction hardware
- algorithm implementation for CDFG pipelining


Interested parties are welcome to contact me for details on how to get
access to a demo version of the YARDstick toolset.


Kind regards

Nikolaos Kavvadias
Computer Architecture Specialist - Compiler Developer
Ph.D. candidate
M.Sc. Eletronics Engineering
B.Sc. Physics

You may contact me at:
Nikolaos Kavvadias <[email protected]>
http://www.geocities.com/kaveirious/
http://electronics.physics.auth.gr/tomeas/en/kavvadias.html
 
J

JeffM

Uncle said:
ANNOUNCE: YARDstick - custom processor development toolset
[chest thumping snipped]

FTFP:

Downloads
1. A 2-page abstract describing YARDstick
2. Short presentation of YARDstick
3. A 2-page brochure on YARDstick
4. In the near future,
YARDstick binaries will be made available for download!
 
U

Uncle Noah

4. In the near future,
YARDstick binaries will be made available for download!

Hey JeffM

YARDstick is real and is working. However, i'm in the process of
taking care of the legalese for the whole thing.

But why do you believe that is vapor? Can't you believe that it is the
work of a single man, (2.5 man/years of on-and-off work) measuring
about 25Klines of C, C++ and Tcl/Tk code?

Do you use Graphviz or VCG or are you just a bozzo, that is not aware
of the tools?

Check out a custom instruction from an edge detection filter.

VCG dump:

graph: { title: "main_9"

x: 30
y: 30
height: 380
width: 560
xspace: 20
yspace: 30
display_edge_labels: yes
layoutalgorithm: minbackward
port_sharing: no
node.borderwidth: 3
node.color: white
node.textcolor: black
node.bordercolor: black
edge.color: black

node: { title:"0" shape: ellipse label:" ior" color:yellow }
node: { title:"1" shape: ellipse label:" sl" color:yellow }
node: { title:"2" shape: ellipse label:" abs" color:yellow }
node: { title:"3" shape: ellipse label:" sub" color:yellow }
node: { title:"4" shape: ellipse label:" sl" color:yellow }
node: { title:"5" shape: ellipse label:" abs" color:yellow }
node: { title:"6" shape: ellipse label:" sub" color:yellow }
node: { title:"7" shape: ellipse label:" ldc" color:yellow }
node: { title:"8" shape: rhomb label:" 1" color:magenta }
edge: {sourcename:"8" targetname:"7"}
node: { title:"9" shape: triangle label:" vr234.s32" color:cyan }
edge: {sourcename:"0" targetname:"9"}
node: { title:"10" shape: triangle label:" vr235.s32" color:cyan }
edge: {sourcename:"7" targetname:"10"}
node: { title:"11" shape: box label:" vr60.s32" color:green }
edge: {sourcename:"11" targetname:"1"}
node: { title:"12" shape: box label:" vr207.s32" color:green }
edge: {sourcename:"12" targetname:"3"}
node: { title:"13" shape: box label:" vr210.s32" color:green }
edge: {sourcename:"13" targetname:"3"}
edge: {sourcename:"11" targetname:"4"}
edge: {sourcename:"12" targetname:"6"}
node: { title:"14" shape: box label:" vr220.s32" color:green }
edge: {sourcename:"14" targetname:"6"}

edge: {sourcename:"3" targetname:"2" label:"vr228.s32" }
edge: {sourcename:"2" targetname:"1" label:"vr229.s32" }
edge: {sourcename:"1" targetname:"0" label:"vr230.s32" }
edge: {sourcename:"6" targetname:"5" label:"vr231.s32" }
edge: {sourcename:"5" targetname:"4" label:"vr232.s32" }
edge: {sourcename:"4" targetname:"0" label:"vr233.s32" }

}

Graphviz dump:
digraph main_9 {

node [fontname=Courier,fontsize=14,style=filled];
0 [shape=ellipse,label="ior",fillcolor=yellow]
1 [shape=ellipse,label="sl",fillcolor=yellow]
2 [shape=ellipse,label="abs",fillcolor=yellow]
3 [shape=ellipse,label="sub",fillcolor=yellow]
4 [shape=ellipse,label="sl",fillcolor=yellow]
5 [shape=ellipse,label="abs",fillcolor=yellow]
6 [shape=ellipse,label="sub",fillcolor=yellow]
7 [shape=ellipse,label="ldc",fillcolor=yellow]
8 [shape=diamond,label="1",fillcolor=magenta]
8 -> 7;
9 [shape=triangle,label="vr234.s32",fillcolor=cyan]
0 -> 9;
10 [shape=triangle,label="vr235.s32",fillcolor=cyan]
7 -> 10;
11 [shape=invtriangle,label="vr60.s32",fillcolor=green]
11 -> 1;
12 [shape=invtriangle,label="vr207.s32",fillcolor=green]
12 -> 3;
13 [shape=invtriangle,label="vr210.s32",fillcolor=green]
13 -> 3;
11 -> 4;
12 -> 6;
14 [shape=invtriangle,label="vr220.s32",fillcolor=green]
14 -> 6;

3 -> 2 [label="vr228.s32"];
2 -> 1 [label="vr229.s32"];
1 -> 0 [label="vr230.s32"];
6 -> 5 [label="vr231.s32"];
5 -> 4 [label="vr232.s32"];
4 -> 0 [label="vr233.s32"];

}


Just copy-paste the stuff and use Graphviz (dot) and VCG to view
them.

Can you do that?

Nikolaos Kavvadias
Computer Architecture Specialist and Compiler Developer
Ph.D. candidate
 
U

Uncle Noah

Well man.

I'm just polishing YARDstick and taking care of the legalese. It is a
major project of mine that measures up to ~25klines of code for now,
not to mention the external BSD-licensed libraries it uses.

I can't understand your attitude though. A great automation is not
vapor, but you are.

YARDstick was presented at DATE'07 this April. Some guys from the
MORPHEUS project as well as a senior researcher from Synopsys had a
good look on the tool and its Tcl/Tk 8.5.a5 GUI.

Maybe you should ask MORPHEUS people, they have witnessed it.

Here follows part of my answer to the other post.


Check out a custom instruction from an edge detection filter. It has
been auto-identified and auto-dumped.

VCG dump:

graph: { title: "main_9"

x: 30
y: 30
height: 380
width: 560
xspace: 20
yspace: 30
display_edge_labels: yes
layoutalgorithm: minbackward
port_sharing: no
node.borderwidth: 3
node.color: white
node.textcolor: black
node.bordercolor: black
edge.color: black

node: { title:"0" shape: ellipse label:" ior" color:yellow }
node: { title:"1" shape: ellipse label:" sl" color:yellow }
node: { title:"2" shape: ellipse label:" abs" color:yellow }
node: { title:"3" shape: ellipse label:" sub" color:yellow }
node: { title:"4" shape: ellipse label:" sl" color:yellow }
node: { title:"5" shape: ellipse label:" abs" color:yellow }
node: { title:"6" shape: ellipse label:" sub" color:yellow }
node: { title:"7" shape: ellipse label:" ldc" color:yellow }
node: { title:"8" shape: rhomb label:" 1" color:magenta }
edge: {sourcename:"8" targetname:"7"}
node: { title:"9" shape: triangle label:" vr234.s32" color:cyan }
edge: {sourcename:"0" targetname:"9"}
node: { title:"10" shape: triangle label:" vr235.s32" color:cyan }
edge: {sourcename:"7" targetname:"10"}
node: { title:"11" shape: box label:" vr60.s32" color:green }
edge: {sourcename:"11" targetname:"1"}
node: { title:"12" shape: box label:" vr207.s32" color:green }
edge: {sourcename:"12" targetname:"3"}
node: { title:"13" shape: box label:" vr210.s32" color:green }
edge: {sourcename:"13" targetname:"3"}
edge: {sourcename:"11" targetname:"4"}
edge: {sourcename:"12" targetname:"6"}
node: { title:"14" shape: box label:" vr220.s32" color:green }
edge: {sourcename:"14" targetname:"6"}

edge: {sourcename:"3" targetname:"2" label:"vr228.s32" }
edge: {sourcename:"2" targetname:"1" label:"vr229.s32" }
edge: {sourcename:"1" targetname:"0" label:"vr230.s32" }
edge: {sourcename:"6" targetname:"5" label:"vr231.s32" }
edge: {sourcename:"5" targetname:"4" label:"vr232.s32" }
edge: {sourcename:"4" targetname:"0" label:"vr233.s32" }

}

Graphviz dump:
digraph main_9 {

node [fontname=Courier,fontsize=14,style=filled];
0 [shape=ellipse,label="ior",fillcolor=yellow]
1 [shape=ellipse,label="sl",fillcolor=yellow]
2 [shape=ellipse,label="abs",fillcolor=yellow]
3 [shape=ellipse,label="sub",fillcolor=yellow]
4 [shape=ellipse,label="sl",fillcolor=yellow]
5 [shape=ellipse,label="abs",fillcolor=yellow]
6 [shape=ellipse,label="sub",fillcolor=yellow]
7 [shape=ellipse,label="ldc",fillcolor=yellow]
8 [shape=diamond,label="1",fillcolor=magenta]
8 -> 7;
9 [shape=triangle,label="vr234.s32",fillcolor=cyan]
0 -> 9;
10 [shape=triangle,label="vr235.s32",fillcolor=cyan]
7 -> 10;
11 [shape=invtriangle,label="vr60.s32",fillcolor=green]
11 -> 1;
12 [shape=invtriangle,label="vr207.s32",fillcolor=green]
12 -> 3;
13 [shape=invtriangle,label="vr210.s32",fillcolor=green]
13 -> 3;
11 -> 4;
12 -> 6;
14 [shape=invtriangle,label="vr220.s32",fillcolor=green]
14 -> 6;

3 -> 2 [label="vr228.s32"];
2 -> 1 [label="vr229.s32"];
1 -> 0 [label="vr230.s32"];
6 -> 5 [label="vr231.s32"];
5 -> 4 [label="vr232.s32"];
4 -> 0 [label="vr233.s32"];

}


Just copy-paste the stuff and use Graphviz (dot) and VCG to view
them.

Nikolaos Kavvadias
Computer Architecture Specialist and Compiler Developer
Ph.D. candidate
 
U

Uncle Noah

Sorry, forgot the ANSI C simulation code for the custom instruction.

Here it is:

void ci_9(
int *d0
,int *d1
,int s0
,int s1
,int s2
,int s3
)
{
int vr228_s32;
int vr229_s32;
int vr230_s32;
int vr231_s32;
int vr232_s32;
int vr233_s32;
*d1 = 1;
vr231_s32 = s1-s3;
vr232_s32 = ((vr231_s32 < 0) ? -vr231_s32 : vr231_s32);
vr233_s32 = s0<vr232_s32;
vr228_s32 = s1-s2;
vr229_s32 = ((vr228_s32 < 0) ? -vr228_s32 : vr228_s32);
vr230_s32 = s0<vr229_s32;
*d0 = vr230_s32|vr233_s32;
#pragma cycles_est_total = 2
}

Now, can you see the power of YARDstick?

My backend generating fully ANSI C simulation code for any custom
instruction (of any complexity within basic block limits -- for now)
is a mere 1000 lines in C.

Again: what is that you find inconceivable (or impossible). I have
been using YARDstick for 6 months now, and continue to maintain and
add useful stuff to it.

By the time of the DATE'07 conference, the source code base was around
16Klines.

Hope you can see that is doable by a very good programmer with a good
deal of architecture depth (this is me ^_^)

Nikolaos Kavvadias
Computer Architecture Specialist and Compiler Developer
Ph.D. candidate
 
E

Evan Lavelle

Again: what is that you find inconceivable (or impossible). I have
been using YARDstick for 6 months now, and continue to maintain and
add useful stuff to it.

By the time of the DATE'07 conference, the source code base was around
16Klines.

Hope you can see that is doable by a very good programmer with a good
deal of architecture depth (this is me ^_^)

He didn't say it wasn't doable, or inconceivable; he said he couldn't
download it. If he got the link wrong, perhaps you should give him
another link.
 
U

Uncle Noah

He didn't say it wasn't doable, or inconceivable; he said he couldn't
download it. If he got the link wrong, perhaps you should give him
another link.

Hi Evan

thanks for clearing this up.

Here is the whole story:
i would release a binary version of YARDstick only under the following
circumstances:
.... if i had a steady job. I'm 30 and looking for a decent engineering/
research job in Greece or the EU. It seems here that opportunities are
quite limited for real state-of-the-art research, developing
prototypes and pushing some good stuff into the market. Let's say that
within the university that i had contract from period to period (with
extremely low payment) and got wildly exploited for it. For example, i
have developed really nice FPGA lab exercises (a messaging machine and
an embedded processor running edge detection) for $0 payment. I have
supervised over 15 BSc and Msc theses as well as supervised zillions
of exam hours for $0 payment.
ENOUGH!

Since i have no job, and no insurance, i will release nothing to
noone.
Zero, nothing, nil, zip.

If there appears to be some real interest, from real people (and not
let's say academic bozzos), i will setup a CGI-driven site so it could
be accessed online. And this will only be for a small period of time,
just to so what it can do to the interested parties.

I have particularly used my code with BSD-licensed stuff so i will not
have to release anything.

So to sum up, things changed since last April. I thought i would get a
job within a university facility (a research staff position).

Kind regards
Nikolaos Kavvadias
 
U

Uncle Noah

Hey JeffM

i don't see you responding, about the uploaded some sample auto-
generated files for a custom instruction.
What is your opinion?

You made a hasty choice to rename the thread. Shame on you and the
other academic bozzos out there. All you people teach youngsters (i'm
over 30, i'm no toy-boy) holy pieces of crap like top-down
programming, UML-powered or not.

And is another thing to teach science matters, all fine by me, and
wildly another to take a certain rotten point of view on applying
certain processes for problem understanding and solving.

You waste precious taxpayers money! Do parents know what are young
wanna-be engineers taught in their courses?

Are they taught scientific matters or waste hours of their lifes on
what their prof. is good at (since his Ph.D. days?)

I have two crappy degrees on Physics, and Applications of Physics in
Electronics (the second with honors). They are junk, as i work on what
i have taught myself since 2000.

Shame on you people! Have you ever coded a piece of working software?
Anything beyond the first couple of thousand lines?

BTW: What is your opinion on the auto-generated files? (having a few
good laughs with academic bozzos, playing hardball in courses).

Nikolaos Kavvadias
 
F

FreeRTOS.org

Uncle Noah said:
Hey JeffM

i don't see you responding, about the uploaded some sample auto-
generated files for a custom instruction.
What is your opinion?


I'm not really following this thread. Are you announcing that something is
available, or that something is not available?
You made a hasty choice to rename the thread. Shame on you and the
other academic bozzos out there. All you people teach youngsters (i'm
over 30, i'm no toy-boy) holy pieces of crap like top-down
programming, UML-powered or not.

<snip>

Do you know Werty?

--
Regards,
Richard.

+ http://www.FreeRTOS.org
13 official architecture ports, 1000 downloads per week.

+ http://www.SafeRTOS.com
Certified by TÜV as meeting the requirements for safety related systems.
 
S

Shannon

Hey JeffM

i don't see you responding, about the uploaded some sample auto-
generated files for a custom instruction.
What is your opinion?

You made a hasty choice to rename the thread. Shame on you and the
other academic bozzos out there. All you people teach youngsters (i'm
over 30, i'm no toy-boy) holy pieces of crap like top-down
programming, UML-powered or not.

And is another thing to teach science matters, all fine by me, and
wildly another to take a certain rotten point of view on applying
certain processes for problem understanding and solving.

You waste precious taxpayers money! Do parents know what are young
wanna-be engineers taught in their courses?

Are they taught scientific matters or waste hours of their lifes on
what their prof. is good at (since his Ph.D. days?)

I have two crappy degrees on Physics, and Applications of Physics in
Electronics (the second with honors). They are junk, as i work on what
i have taught myself since 2000.

Shame on you people! Have you ever coded a piece of working software?
Anything beyond the first couple of thousand lines?

BTW: What is your opinion on the auto-generated files? (having a few
good laughs with academic bozzos, playing hardball in courses).

Nikolaos Kavvadias

WOW! Not bitter at all! Um I think someone needs to take a little
nappy.

I think you need to work on your sales pitch a little Nikolaos. I was
going to look at what you've done but you seem to belittle everything
I've done in my career as well as most of my academic friends. Don't
think I want to look at your little project at all now.

Shannon
 
U

Uncle Noah

I think you need to work on your sales pitch a little Nikolaos. I was
going to look at what you've done but you seem to belittle everything
I've done in my career as well as most of my academic friends. Don't
think I want to look at your little project at all now.

Shannon

Hi Shannon

it sounds that i'm bitter against all academic people around, but is
only a tiny fraction of them that i'm mad at.

however it seems that i have touched a sensitive chord here. the truth
always hurts. it might be an extravagant and colorful view of mine, i
guess.

now, about my project. Are you (or any colleague of yours with
practical interests in field) interested in it?

Kind regards
Nikolaos Kavvadias
 
U

Uncle Noah

I'm not really following this thread. Are you announcing that something is
available, or that something is not available?

I'm announcing the existence of the YARDstick tool. It is in a good
state for real use.
You know that (let's say) CorelDray started from version 1.0 and not
11.0... ^_^.

But i'm angry for him renaming this thread. I have never, ever,
renamed a thread, whatever i was thinking of it.
Do you know Werty?

And i donnot know Werty.
 

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