N
Nikolaos Kavvadias
Dear all,
I hope you are doing well.
Just wanted to let you know that I've uploaded one of my first "serious" designs passed through HercuLeS HLS: http://www.nkavvadias.com/hercules/
This was around 2010, and it was an HLS showcase for a partner/client in Europe. I can finally distribute the test case freely so here you are:
http://www.opencores.org/project,kvcordic
Description:
The design is a universal CORDIC IP core supporting all directions (ROTATION,
VECTORING) and modes (CIRCULAR, LINEAR, HYPERBOLIC). The I/O interface is similar to e.g. the CORDIC IP generated by Xilinx Core Generator). It provides three data inputs (xin,yin, zin) and three data outputs (xout,yout, zout) as well as the direction and mode control inputs. The testbench will testthe core for computing cos (xin), sin (yin), arctan(yin/xin), yin/xin, √w, 1/√w, with
xin = w + 1/4, yin = w − 1/4, but it can be used for anything computable by CORDIC iterations. The computation of 1/√w is performed in two stages: a) y = 1/w, b) z = √y.
The design is a monolithic FSMD that does not include post-processing needed such as the scaling operation for the square root. The FSMD for the CORDIC uses Q2.14 ï¬xed-point arithmetic. The core achieves 18 (CIRCULAR,LINEAR) and 19 cycles (HYPERBOLIC) per sample or n + 4 and n + 5 cycles, respectively, where n is the fractional bitwidth. A single-cycle per iteration constraint imposes the
use of distributed LUT RAM, otherwise 3 cycles are required per sample (distinct load, compute, store cycles).
SPECIAL THANKS: Go to MSc and PhD candidate Mrs. Vasiliki Giannakopoulou for explaining to me how CORDIC works and for implementing a hand-coded optimized version to compare with! Her hand-written CORDIC is also blazing fast for a portable non-Xilinx or non-Altera specific design.
Best regards,
Nikolaos Kavvadias
Independent Research Scientist / Hardware engineer / EDA developer
http://www.nkavvadias.com
Lamia, Greece
I hope you are doing well.
Just wanted to let you know that I've uploaded one of my first "serious" designs passed through HercuLeS HLS: http://www.nkavvadias.com/hercules/
This was around 2010, and it was an HLS showcase for a partner/client in Europe. I can finally distribute the test case freely so here you are:
http://www.opencores.org/project,kvcordic
Description:
The design is a universal CORDIC IP core supporting all directions (ROTATION,
VECTORING) and modes (CIRCULAR, LINEAR, HYPERBOLIC). The I/O interface is similar to e.g. the CORDIC IP generated by Xilinx Core Generator). It provides three data inputs (xin,yin, zin) and three data outputs (xout,yout, zout) as well as the direction and mode control inputs. The testbench will testthe core for computing cos (xin), sin (yin), arctan(yin/xin), yin/xin, √w, 1/√w, with
xin = w + 1/4, yin = w − 1/4, but it can be used for anything computable by CORDIC iterations. The computation of 1/√w is performed in two stages: a) y = 1/w, b) z = √y.
The design is a monolithic FSMD that does not include post-processing needed such as the scaling operation for the square root. The FSMD for the CORDIC uses Q2.14 ï¬xed-point arithmetic. The core achieves 18 (CIRCULAR,LINEAR) and 19 cycles (HYPERBOLIC) per sample or n + 4 and n + 5 cycles, respectively, where n is the fractional bitwidth. A single-cycle per iteration constraint imposes the
use of distributed LUT RAM, otherwise 3 cycles are required per sample (distinct load, compute, store cycles).
SPECIAL THANKS: Go to MSc and PhD candidate Mrs. Vasiliki Giannakopoulou for explaining to me how CORDIC works and for implementing a hand-coded optimized version to compare with! Her hand-written CORDIC is also blazing fast for a portable non-Xilinx or non-Altera specific design.
Best regards,
Nikolaos Kavvadias
Independent Research Scientist / Hardware engineer / EDA developer
http://www.nkavvadias.com
Lamia, Greece