S
Steffen Koepf
Hello,
i have a cyclone III device with a synchronous design in it.
Now i need a external memory interface to a ATMega, where
the ATMega is the master. The ATMega uses the ALE/-Wr/-Rd
style interface also used in the MCS51 devices.
The problem is, that the lower address data are only valid
for at least 5 ns after a falling edge of ALE. So i cant
synchronise the ALE signal in my internal 100 MHz clock domain.
Is it possible, to use a User-IO Pin for the ALE signal like
this:
ale : process (ExtBusALE)
begin
if (falling_edge(ExtBusALE) ) then
BusAddrInt(15 downto 8) <= ExtBusAddress(15 downto 8);
BusAddrInt(7 downto 0) <= ExtBusAD;
end if;
end process;
to store the address data at a falling ALE edge?
If not, is it possible to use a dedicated clock input for
ALE, so that the signal is distributed to the clock inputs
of the BusAddrInt storing registers?
Thanks in advance,
Steffen
i have a cyclone III device with a synchronous design in it.
Now i need a external memory interface to a ATMega, where
the ATMega is the master. The ATMega uses the ALE/-Wr/-Rd
style interface also used in the MCS51 devices.
The problem is, that the lower address data are only valid
for at least 5 ns after a falling edge of ALE. So i cant
synchronise the ALE signal in my internal 100 MHz clock domain.
Is it possible, to use a User-IO Pin for the ALE signal like
this:
ale : process (ExtBusALE)
begin
if (falling_edge(ExtBusALE) ) then
BusAddrInt(15 downto 8) <= ExtBusAddress(15 downto 8);
BusAddrInt(7 downto 0) <= ExtBusAD;
end if;
end process;
to store the address data at a falling ALE edge?
If not, is it possible to use a dedicated clock input for
ALE, so that the signal is distributed to the clock inputs
of the BusAddrInt storing registers?
Thanks in advance,
Steffen