Hi,\n\nI'm trying to code a bit stuffing entity with serial input/output\n(i.e. input="1", then output = "10", input="0", then output "00"), all\nsynchronized by clock. At the moment i only know the following\noptions:\n\n1. Use rising and falling edge of the clock to output 2 bits (original\nbit and stuff bit) in one period -> Not synthetizable\nwith Xilinx.\n2. Use a FSM with an internal buffer where input is stored. In that\ncase how I can avoid buffer overflow if i don't know the input\nlengtht?\n\nPlease tell me if someone have some ideas about how to implement\nserial bit stuffing in vhdl.\n\nThanks in advance.