bit stuffing

Discussion in 'VHDL' started by blackpadme, Aug 24, 2008.

  1. blackpadme

    blackpadme Guest


    I'm trying to code a bit stuffing entity with serial input/output
    (i.e. input="1", then output = "10", input="0", then output "00"), all
    synchronized by clock. At the moment i only know the following

    1. Use rising and falling edge of the clock to output 2 bits (original
    bit and stuff bit) in one period -> Not synthetizable
    with Xilinx.
    2. Use a FSM with an internal buffer where input is stored. In that
    case how I can avoid buffer overflow if i don't know the input

    Please tell me if someone have some ideas about how to implement
    serial bit stuffing in vhdl.

    Thanks in advance.
    blackpadme, Aug 24, 2008
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  2. blackpadme

    Muzaffer Kal Guest

    The first option is not only synthesizable but also unusable because
    you will change the bit rate at the output. Someone has to consume the
    extra bit and that someone probably be running on a single edge of the
    clock only.

    You should use the second option and implement flow control at the
    input. This means you have to tell the producer of the bits you don't
    have any more buffer space to accept incoming data. Then you can have
    a fixed size buffer, fill it up with extra bits and when it's full
    stop incoming data and send what you have accumulated already. Another
    option is to find out the maximum size of the transmission data (ie
    packet size) and size your buffer to that and send all the accumulated
    stuffed bits at the end.
    What is your actual application? I have implemented bit-stuffing and
    other protocol management functions for a variety of serial
    interfaces. If you can tell me what yours is, I maybe able to help

    Muzaffer Kal, Aug 25, 2008
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  3. This makes no sense unless it is a homework problem.
    Serial bit stuffing is used by an hdlc or usb transmitter
    to packetize data. Just inserted a zero after every bit
    has no obvious application."need+bit+stuffing"
    Packetize the data.

    -- Mike Treseler
    Mike Treseler, Aug 25, 2008
  4. It is, if properly done. But what will you do with the gained DDR
    data? You do such a thing typically only on output pins of your
    device. The problem is something that requires no fpga designer in the
    first place but a system designer. You should first clarify the input
    and output (frequency, packet or stream,...) that your device need to
    produce, before you could start with fpga design.
    This task is generally spoken impossible without further constraining
    of the requirements.

    bye Thomas
    Thomas Stanka, Aug 25, 2008
  5. Hello,
    I have trouble seeing an application for this, but ok. If you're not able to use
    a clock with a higher frequency, then consider using a combinatorial output:

    io_reg: PROCESS IS
    WAIT UNTIL clk = '1';
    input_i <= input;
    END PROCESS io_reg;

    output <= input_i WHEN clk = '1' ELSE '0';

    or alternatively:

    output <= input_i AND clk;

    Kind regards,

    Pieter Hulshoff
    Pieter Hulshoff, Aug 25, 2008
  6. blackpadme

    blackpadme Guest

    Hi, I'm trying insert 0s between inputs because i need a delay at the
    input of a filter. I pretend to use this entity (with some
    modifications) to implement a two's complement encoder too (i.e. x =
    0, y = 11 (-1) and if x = 1, y = 01 (+1)).
    blackpadme, Aug 25, 2008
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