Mixer-Unit on Altera DE2-115 Cyclone IV

Discussion in 'VHDL' started by Larinayo, Dec 28, 2016.

  1. Larinayo

    Larinayo

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    Dec 28, 2016
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    Hello
    I'm supposed to add to parallel 16-bits audio signals into a mixer-unit , then run the resulting signal through a parallel 2 serial unit , got 16 errors while trying to use srl functions and other stuff , could you please help ? My deadline is in 2 days , after the code you will find a picture of the errors => http://imgur.com/a/XD7bi
    Code (Text):
    -----------------------------------------------------------
    --     Institute of Microelectronic Systems
    --     Architectures and Systems
    --     Leibniz Universitaet Hannover
    -----------------------------------------------------------
    --     lab :             Design Methods for FPGAs
    --    file :            mixer_unit.vhdl
    --    authors :      
    --    last update :  
    --    description :  
    -----------------------------------------------------------

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    library work;
    use work.fpga_audiofx_pkg.all;

    entity mixer_unit is
        port (
            clock          : in  std_ulogic;
            reset        : in  std_ulogic;
            -- serial audio-data inputs
            ain_sync    : in  std_ulogic_vector(1 downto 0);
            ain_data    : in  std_ulogic_vector(1 downto 0);
            -- serial audio-data output
            aout_sync    : out std_ulogic;
            aout_data    : out std_ulogic;
            -- Mono
            mono       : out std_ulogic_vector(16 downto 0);
            -- serial mono
            Serialmono  : out std_ulogic
                 );
    end mixer_unit;


    architecture rtl of mixer_unit is


    component s2p_unit is
        port (
            clock          : in  std_ulogic;
            reset        : in  std_ulogic;
            -- serial audio-data signals
            ain_sync    : in  std_ulogic;
            ain_data    : in  std_ulogic;
            -- parallel audio-data signals
            smp_valid    : out std_ulogic;
            smp_ack        : in  std_ulogic;
            smp_data    : out std_ulogic_vector(15 downto 0)
        );
    end component s2p_unit;

    component p2s_unit is
        port (
            clock          : in  std_ulogic;
            reset        : in  std_ulogic;
            -- parallel audio-data signals
            smp_valid     : in  std_ulogic;
            smp_ack       : out std_ulogic;
            smp_data      : in  std_ulogic_vector(SAMPLE_WIDTH-1 downto 0);
            -- serial audio-data signals
            aout_sync     : out std_ulogic;
            aout_data     : out std_ulogic
        );
    end component p2s_unit;

    signal ain_left_sync     : std_ulogic;
    signal ain_left_data     : std_ulogic;
    signal ain_right_sync     : std_ulogic;
    signal ain_right_data     : std_ulogic;

    signal test_valid_right : std_ulogic;
    signal test_ack_right : std_ulogic;
    signal test_valid_left: std_ulogic;
    signal test_ack_left : std_ulogic;
    signal aout_left_data : std_ulogic_vector(15 downto 0);
    signal aout_right_data : std_ulogic_vector(15 downto 0);



    begin
    mono<= srl(aout_left_data,1) + srl(aout_right_data,1);
    serialmono<= p2s_unit(mono);


    S2P_left: s2p_unit port map (
    clock => clock,
    reset => reset,
    ain_sync => ain_left_sync,
    ain_data => ain_left_data,
    smp_valid => test_valid_left ,
    smp_ack => test_ack_left ,
    smp_data => aout_left_data

    );

    S2P_right: s2p_unit port map (
    clock => clock,
    reset => reset,
    ain_sync => ain_right_sync,
    ain_data => ain_right_data,
    smp_valid => test_valid_right ,
    smp_ack => test_ack_right ,
    smp_data => aout_right_data


    );
    P2S: p2s_unit port map (
            clock => clock,
            reset => reset,
            -- serial audio-data inputs
            smp_valid => smp_valid,
            smp_ack   => smp_ack,
            smp_data  => smp_data,
            -- serial audio-data output
            aout_sync => aout_sync,
            aout_data => aout_data,
            mono => mono,
            serialmono => serialmono
    );
    end architecture rtl;

    ;)
     
     
    Larinayo, Dec 28, 2016
    #1
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