error in serial right operation in modelsim10.4a

Discussion in 'VHDL' started by maneesha zakka, Oct 8, 2015.

  1. maneesha zakka

    maneesha zakka

    Oct 5, 2015
    Likes Received:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    entity convert is
    port(a:in std_ulogic_vector(0 to 15);s:eek:ut std_ulogic_vector(0 to 15));
    end convert;
    architecture convert of convert is
    signal r,b,x,q:std_ulogic_vector(0 to 15);
    for i in 0 to 15 loop--here error is Illegal concurrent statement.
    s(i)<=x and b;//error is Target type ieee.std_logic_1164.STD_ULOGIC in signal assignment is different from expression type ieee.std_logic_1164.STD_LOGIC_VECTOR.
    x<= x srl 1; //error is No feasible entries for infix operator "srl",ype error resolving infix expression "srl" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
    end loop;
    end convert;
    --is simulated in modelsim10.4a.can anyone help me in resolving this errors.
    maneesha zakka, Oct 8, 2015
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