P
Paul
Hi,
in the example attached I did try to parametrize my fir filter (direct
form I second order structure) internal signals. Modelsim complains on
it and I have no idea why and how to fix it. Anyway, the idea behind
should be clear.
Thanks,
Olaf
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library floatfixlib;
use floatfixlib.math_utility_pkg.all; -- ieee_proposed for VHDL-93 version
use floatfixlib.fixed_pkg.all; -- ieee_proposed for compatibility version
entity df1tsos is
generic(
numerator: sfixed := sfixed(16 downto -14); -- [-2 2)
denominator: sfixed := sfixed(16 downto -14); -- [-2 2)
numerator_state: sfixed := sfixed(16 downto -12); -- [-8 8)
denominator_state: sfixed := sfixed(16 downto -12) -- [-8 8)
);
port (
clk : in std_ulogic;
clk_en : in std_ulogic;
reset : in std_ulogic;
input : in sfixed(16 downto -14); -- [-2 2)
output : out sfixed(16 downto -14) -- [-2 2)
);
end entity df1tsos;
architecture rtl of df1tsos is
subtype numerator_type is sfixed range numerator'high downto
numerator'low;
begin
end architecture rtl;
in the example attached I did try to parametrize my fir filter (direct
form I second order structure) internal signals. Modelsim complains on
it and I have no idea why and how to fix it. Anyway, the idea behind
should be clear.
Thanks,
Olaf
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library floatfixlib;
use floatfixlib.math_utility_pkg.all; -- ieee_proposed for VHDL-93 version
use floatfixlib.fixed_pkg.all; -- ieee_proposed for compatibility version
entity df1tsos is
generic(
numerator: sfixed := sfixed(16 downto -14); -- [-2 2)
denominator: sfixed := sfixed(16 downto -14); -- [-2 2)
numerator_state: sfixed := sfixed(16 downto -12); -- [-8 8)
denominator_state: sfixed := sfixed(16 downto -12) -- [-8 8)
);
port (
clk : in std_ulogic;
clk_en : in std_ulogic;
reset : in std_ulogic;
input : in sfixed(16 downto -14); -- [-2 2)
output : out sfixed(16 downto -14) -- [-2 2)
);
end entity df1tsos;
architecture rtl of df1tsos is
subtype numerator_type is sfixed range numerator'high downto
numerator'low;
begin
end architecture rtl;