J
jacko
hi
done quite a lot http://indi.hpsdr.com
mode 4 PIO disk controller
io ports
MAXII ufm
all wishbone compliant (except i did not use the CYC_I bus pin, and
added a HLT_I (halt) bus pin.
was not sure if the CYC_I pin could be used as a not halt pin, and i
will decode address space on STB_I pin enable.
i seem to be confused about the need for CYC_I, and any benefit that
LOCK_I would provide over CYC_I. The pin is present on the interface
but not used in the vhdl.
Also i had to mash together the memdrv.vhd memory driver to interleave
read and possible write cycles to maximize memory bandwidth, with the
write follows write problem of not releasing R/W and needing to
release to store. good for me the memory on the devkit needs no
address hold times
ok cheers
done quite a lot http://indi.hpsdr.com
mode 4 PIO disk controller
io ports
MAXII ufm
all wishbone compliant (except i did not use the CYC_I bus pin, and
added a HLT_I (halt) bus pin.
was not sure if the CYC_I pin could be used as a not halt pin, and i
will decode address space on STB_I pin enable.
i seem to be confused about the need for CYC_I, and any benefit that
LOCK_I would provide over CYC_I. The pin is present on the interface
but not used in the vhdl.
Also i had to mash together the memdrv.vhd memory driver to interleave
read and possible write cycles to maximize memory bandwidth, with the
write follows write problem of not releasing R/W and needing to
release to store. good for me the memory on the devkit needs no
address hold times
ok cheers