C/C++ Hardware modelling

[sun]

Hello All,
I wanted to develop a hardware model in C/C++ but iam not sure about
the procedure, can any one help me out by providing some guidlines for
developing or pointing to some wepage where i can get some guidlines or
some sample C/C++ codes for a hardware model.

Sun

 

[Ian Collins]

Hello All,
I wanted to develop a hardware model in C/C++ but iam not sure about
the procedure, can any one help me out by providing some guidlines for
developing or pointing to some wepage where i can get some guidlines or
some sample C/C++ codes for a hardware model.

What exactly do you wish to model?

 

[sun]

Hello Collins,
Thanks for your reply... actually i wanted to model a ethernet
packet interface, which can act as a transmitter or an receiver ,
during the transmitter mode, the c/c++ mode has to read data from a RAM
model and add the header information and transmit the packet, in the
receiver mode, the packet interface will receive the packet removes the
header information and seperates the data alone and store in a ram
model.
The c/c++ model has some internal register setting based on the
internal register setting the model has to work. Now i need to know how
to model the register setting in the c/c++, also iam not having much
idea of how the control data transfer between modules will happen in
c/c++, it would be better if you can give some ideas.

 

[PraZ]

Try searching for System C.

 

[sun]

Hello Praz,
Thanks for your reply.... and it would be better if i go in
SystemC, but the requirement is to model purely in c/c++, i am not
having much issues imodelling in HDL like verilog, vhdl, systemverilog
or in SystemC, but the requirement is to model in c/c++ which i have
not done before... so it would be great if you can give me some ideas
in modelling in c/c++.

 

[prasanna.sethuraman]

typedef int int32;

class Register {

private:
int32 reg;

int32 Read() { return reg; };
int32 Write( int32 data) { reg = data; };

friend class SystemBus<Register>;

public:
Register() {};
~Register() {};

};

template <class T>
class SystemBus {

public:

SystemBus() {};
~SystemBus() {};

int32 Read() { return T::Read (); };
int32 Write(int32 data) { T::Write(data); };
};

Something like this maybe? And RAM is just a collection of registers.
The class SystemBus should have the bus width as a parameter for its
constructor. The register must be accesible only by writing into the
bus. May be the register class can have a flag which must be set if the
bus has to write into the register. If not, an exception can be
generated. Which busses connect to which can be decided beforehand.

May be there are better ways of doing it. But this is all I could think
of right now. And oh, the C++ code above obviously has syntax errors.
But I am sure you can sort them out.

Hope it is of some help.

 

[prasanna.sethuraman]

typedef int int32;

class Register {

private:
int32 reg;

int32 Read() { return reg; };
int32 Write( int32 data) { reg = data; };

friend class SystemBus<Register>;

public:
Register() {};
~Register() {};

};

template <class T>
class SystemBus {

public:

SystemBus() {};
~SystemBus() {};

int32 Read() { return T::Read (); };
int32 Write(int32 data) { T::Write(data); };
};

Something like this maybe? And RAM is just a collection of registers.
The class SystemBus should have the bus width as a parameter for its
constructor. The register must be accesible only by writing into the
bus. May be the register class can have a flag which must be set if the
bus has to write into the register. If not, an exception can be
generated. Which busses connect to which can be decided beforehand.

May be there are better ways of doing it. But this is all I could think
of right now. And oh, the C++ code above obviously has syntax errors.
But I am sure you can sort them out.

Hope it is of some help.