case statement concatenation condition

[Mark]

One syntax I've favored in verilog for compactness (and to see that
all variable conditions are covered) is to express logic in a truth
table as:

casez( {a,b,c} )
3'b000: z <= ...
3'b001: z <= ...

I'm trying to use a similar style in VHDL, and am wondering if there
is an elegant way to do this. My first attempt was:

case a & b & c is
when "000" => z <= ...
when "001" => z <= ..

With the error, "Ambiguous type in infix expression; unsigned or
signed."

OK. Strong typing... doesn't know what type the concatenation should
resolve to... so I write:

case std_logic_vector'(a & b & c) is
when "000" => z <= ...
when "001" => z <= ..

I get the model sim warning "Array type case expression must be of a
locally static subtype."

I could assign the concatenation first to a variable (verbose), or I
could disabled the warning in modelsim (but it does seem to be a valid
violation of the VHDL language), but does anyone have a suggestion on
how to write this in both a terse and correct way?

Thanks,

Mark

 

[Mark]

You need to be even stronger... the *subtype* of the
case expressions is still not "locally static".  And
yes, it's a pain and everyone agrees it's a pain.  It
just falls out of the language rules like that.

Luckily there's a relatively simple fix.  Declare
a subtype of std_logic_vector (typically in the
declarative region of your process):

  subtype slv3 is std_logic_vector(2 downto 0);

And then you can qualify the case expression with
the locally-static subtype:

  case slv3'(a & b & c) is
    when "000" => ...

and all will be well.

Of course, you may well need rather a lot of such
subtype declarations, if you have numerous different
case statements.

Enjoy
--
Jonathan Bromley, Consultant

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Jonathan,

Thanks! Like that much better than the alternatives I was considering.

Mark