clock divide by 5

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Hi,

I want to generate a clock which is a divide of 5 from an input clock and with symmetrical duty cycle. Can anyone help me with the vhdl codes? I'm new with VHDL.

Thank you.
 
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The following code would give u some idea

The following code explains how to generate a slower clock from a faster clock. That means it is exactly opposite to clock divider. But I think this would give u some idea about how to make the clock divider.


-----------------------------------------------------------------------------
-- Clk Generator
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;


entity clk_gen is
port (
FClk : in std_logic;
SClk : out std_logic

);
end clk_gen;

architecture behavioral of clk_gen is

begin
process (FClk)
VARIABLE temp : std_logic_vector(2 downto 0):= "000";
begin
IF (FClk'event and FClk = '1') THEN
temp := temp + '1';
SClk <= temp(2);
END IF;
end process;
end behavioral;


--FClk means faster clock
--SClk means slower clock
 
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You are not going to get a 50% duty cycle (2.5/5) unless you can first double your clock and then divide by 10. Do you have a PLL available in your IC?
 

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