Content of RAM

[ALuPin]

Hi,

if I want to see the content of external SRAM in simulation (Modelsim)
it is no problem because the memory of the VHDL SRAM model is
represented by an variable field "memdata" which I can visualize in
Modelsim.

But how can I see the complete content of a RAM block (created with
the MegaWizard in QuartusII) in Modelsim ?
The only access to the memory are the ports wraddress, rdaddress ...

Is there a way to look at the content?

Thank you for your help.

Kind regards

 

[Nicolas Matringe]

ALuPin a écrit:

But how can I see the complete content of a RAM block (created with
the MegaWizard in QuartusII) in Modelsim ?
The only access to the memory are the ports wraddress, rdaddress ...

Is there a way to look at the content?

Search for the design unit "altsyncram" in your design hierarchy. Then
open the "process" and "variables" windows. Process 'line__20260' has
two variables called m_mem_data_a and m_meme_data_b which hold the RAM
content

 

[Mike Treseler]

But how can I see the complete content of a RAM block (created with
the MegaWizard in QuartusII) in Modelsim ?
The only access to the memory are the ports wraddress, rdaddress ...

Is there a way to look at the content?

Consider using a synthesis template
rather than a MegaWizard netlist.

http://groups.google.com/groups?q=kwaj+modelsim+waveform+array

-- Mike Treseler

 

[ALuPin]

ALuPin a écrit:


Search for the design unit "altsyncram" in your design hierarchy. Then
open the "process" and "variables" windows. Process 'line__20260' has
two variables called m_mem_data_a and m_meme_data_b which hold the RAM
content

Hi,

I find m_mem_data and m_mem_data_b in
line__17463

Why different number? (I use Altera Modelsim 5.7e / Altera QuartusII v.4.0 SP1)


One more question:

I have the following RAM instantiation:

data
wren
wraddress[14..0]
rdaddress[9..0] q[31..0] (output is not registered)
rden
wrclock
rdclock

m_mem_data shows 32767 positions initialized with '0'.
During simulation I write to position decimal 416 a '1' which
I can see at the corresponding position.
When activating rdaddress and the corresponding rden I get at the
output of my RAM structure a definded value "0000....0001".
But when I have a look at m_mem_data_b all values (0 ..1023) remain 'U'.

What does this m_mem_data_b represent and why do the values remain 'U'?

 

[ALuPin]

Consider using a synthesis template
rather than a MegaWizard netlist.

http://groups.google.com/groups?q=kwaj+modelsim+waveform+array

-- Mike Treseler

Hello Mr Treseler,

you said yome time ago:

"If you have modelsim, just leaving the
mouse arrow over the array waveform will
pop up a box with all values in it.

If you don't, just add something like this
to your testbench:

report "array of ints";
dump : for i in these_ints'range loop
report integer'image(these_ints(i));
end loop dump;"

But what if the array is too large ?
Then I only can see a part of the array, the bottom is marked with "..."
So how can I see other parts of the array when leaving the mouse arrow
over it?

 

[ALuPin]

What is the difference between
a synthesis template and a MegaWizard netlist?