H
Hawker
Hello.
Doing a first design with a Cool Runner II (mostly done 9500 stuff in
the past).
Also first time using the new "Platform Cable USB" programmer. Always
used the Parallel Cable III or IV in the past.
I want to verify that I have VCCAux (the JTAG VCC) correct since I found
three different notes in three different Xilinx Data Sheets.
My CPLD has 2.8V and 3.3 I/O and 1.8V Core. 3.3 is always powered and
1.8 and 2.8 are only powered when the on on board MPU enables them.
I assume I should connect VccAUX to 3.3V and Pin 2 (Vref) of the
Platform Cable USB. It looks like I must have 1.8V enabled to program
the Xilinx. For some reason I thought that I read that with the new
programmer I could program the CPLD without system power applied. Did I
miss something? Somewhere I read to connect VccAUX to JTAG pin 2 (Vref)
for this but the programing cable Data Sheet clearly shows this to be an
input not output drive.
Can someone please clarify that I am connecting this puppy correctly.
Thanx
Hawker
Doing a first design with a Cool Runner II (mostly done 9500 stuff in
the past).
Also first time using the new "Platform Cable USB" programmer. Always
used the Parallel Cable III or IV in the past.
I want to verify that I have VCCAux (the JTAG VCC) correct since I found
three different notes in three different Xilinx Data Sheets.
My CPLD has 2.8V and 3.3 I/O and 1.8V Core. 3.3 is always powered and
1.8 and 2.8 are only powered when the on on board MPU enables them.
I assume I should connect VccAUX to 3.3V and Pin 2 (Vref) of the
Platform Cable USB. It looks like I must have 1.8V enabled to program
the Xilinx. For some reason I thought that I read that with the new
programmer I could program the CPLD without system power applied. Did I
miss something? Somewhere I read to connect VccAUX to JTAG pin 2 (Vref)
for this but the programing cable Data Sheet clearly shows this to be an
input not output drive.
Can someone please clarify that I am connecting this puppy correctly.
Thanx
Hawker