data compression algorithms on FPGA

Discussion in 'VHDL' started by Geronimo Stempovski, May 31, 2007.

  1. Hi there,

    I'm thinking about implementing some data compression algorithms on an FPGA
    (Xilinx Virtex-II) using VHDL. Because speed and FPGA utilization are very
    important in this respect, I'd like to get some basic idea about complexity
    and achieveable speed before starting.

    Does anyone know about existing FPGA- implementations of

    - Run-Length-Encoding (RLE)

    - RLE with Burrows-Wheeler Transformation (BWT)

    - JBIG

    - Lempel-Ziv LZ77

    and the achieved throughput und device utilization? Maybe some details about
    existing ASIC implementations of the above mentioned methods may also
    help...?

    Thanks in advance.



    Regards Gero
     
    Geronimo Stempovski, May 31, 2007
    #1
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  2. We did a schematic implementation of an RLE coder for the XC3100A
    family. It achieved around 85MHz.
    Later we implemented a 150MHz Huffman encoder in Spartan-II.

    Both were rather simple projects.

    Kolja Sulimma
     
    comp.arch.fpga, May 31, 2007
    #2
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  3. thanks for the fast response, what about complexity, i.e. equivalent gate
    count?
     
    Geronimo Stempovski, May 31, 2007
    #3
  4. Next to nothing for the RLE (40 LUTs???). A barrel shifter, a BRAM and
    some logic for the Huffmann.

    Kolja Sulimma
     
    comp.arch.fpga, May 31, 2007
    #4
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