Did VHDL-2008 get lost ?

[hssig]

http://groups.google.com/group/comp...1865faf9?lnk=gst&q=VHDL-2008#bd632ce31865faf9

http://groups.google.com/group/comp...8abc952dc?lnk=gst&q=VHDL2008#98a26bf8abc952dc


Are there any news on VHDL-2008 ?
Whether simulation nor synthesis tools do support it considerably. Do
we users have to draw some kind of chain letter to convince Mentor,
Aldec, Synplicity etc. ?

Cheers,
hssig

 

[Tricky]

http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/38...

http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/5b...

Are there any news on VHDL-2008 ?
Whether simulation nor synthesis tools do support it considerably. Do
we users have to draw some kind of chain letter to convince Mentor,
Aldec, Synplicity etc. ?

Cheers,
hssig

Altera started to support VHDL 2008 features in Quartus 9.1, but these
are mostly syntactical support (no built in fixed point library yet,
not even in Q10)

But the big problem is Mentor. Without their support, 2008 wont be
used much for a while, especially as modelsim is the altera simulator
of choice (given its what altera bundle with quartus).

I thought ActiveHDL was supports 2008?

 

[JimLewis]

Hi Hssig,

Are there any news on VHDL-2008 ?
Whether simulation nor synthesis tools do support it considerably. Do
we users have to draw some kind of chain letter to convince Mentor,
Aldec, Synplicity etc. ?

I think letters are always a good idea as they help vendors assign
priority to tasks they are working on. As a result, be sure to
prioritize the features that mean something to you.

OTOH, I think the 3 you mentioned have been actively working on
their implementation of VHDL-2008. You can see evidence of this
in their documentation.

In release 10.0, Altera mentions VHDL-2008. Xilinx does not seem to
mention implementing anything in VHDL-2008 other than the fixed and
floating point packages.

It would be better to test things out rather than relying on
documentation.
I have some of my and David Bishop's examples that I intend to load so
that people can do that.

Again, letters will encourage them further and help them justify their
investment into the language.

Best,
Jim
SynthWorks VHDL Training

 

[HT-Lab]

Altera started to support VHDL 2008 features in Quartus 9.1, but these
are mostly syntactical support (no built in fixed point library yet,
not even in Q10)

But the big problem is Mentor. Without their support, 2008 wont be
used much for a while, especially as modelsim is the altera simulator
of choice (given its what altera bundle with quartus).

The problem here is not just Mentor, I have been told on several occasions that
Mentor gets very few VHDL2008 request so the lack of support is partly(?) our
fault! I also believe that a contributing factor is that Mentor underestimates
the number of VHDL users and perhaps more worrying they believe we are all
slowly migrating to SystemVerilog......

If you are using VHDL and you are paying maintenance then let Mentor know you
want VHDL2008 support!! It only takes a minute, go to your supportnet page,
raise an SR and say you want VHDL2008 support. Alternatively, email your
distributor and say can I have VHDL2008 support in Modelsim 6.7 please!

I thought ActiveHDL was supports 2008?

Yes they do for more than a year now.

Hans
www.ht-lab.com

 

[Charles Gardiner]

http://groups.google.com/group/comp...1865faf9?lnk=gst&q=VHDL-2008#bd632ce31865faf9

http://groups.google.com/group/comp...8abc952dc?lnk=gst&q=VHDL2008#98a26bf8abc952dc


Are there any news on VHDL-2008 ?
Whether simulation nor synthesis tools do support it considerably. Do
we users have to draw some kind of chain letter to convince Mentor,
Aldec, Synplicity etc. ?

Cheers,
hssig

Aldec Riviera already supports it pretty well. I'm slowly migrating whereever it
makes sense and haven't encountered any difficulties so far.

 

[vipin lal]

Is it possible to create some vote/public letter to convince Mentor,
Aldec and Synplicity.
The VHDL-2008 language develop team can start such a public voting so
that people can show that they want VHDL-2008 support. It will be much
easier this way than individually mailing the above three.

just wondering,is it possible?

 

[hssig]

Is it possible to create some vote/public letter to convince Mentor,
Aldec and Synplicity.
The VHDL-2008 language develop team can start such a public voting so
that people can show that they want VHDL-2008 support. It will be much
easier this way than individually mailing the above three.

just wondering,is it possible?

Excellent idea. Anybody participating in that voting should indicate
her/his function, VHDL affiliation and tool, I think Mentor is the
first vendor to push.
Of course anybody participating should outline the most important
features to be supported. There should be more public courses offered.
In Germany for example
there would be much interest in seeing those courses for VHDL-2008.

Cheers,
hssig

 

[KJ]

Is it possible to create some vote/public letter to convince Mentor,
Aldec and Synplicity.

That vote already occurred. The vote was when the standard was
approved. Mentor and other companies are represented on that public
forum and are participants in the standards development process.

The VHDL-2008 language develop team can start such a public voting so
that people can show that they want VHDL-2008 support.

Petitions are easy and in this case likely to be ineffective. Simply
contact Mentor (and others) directly through their support page and
request implementation of whatever VHDL-2008 features you need the
most and ask them when they're scheduling release of full VHDL-2008.
To gather public interest that might be similar to yours, simply take
whatever you've posted with Mentor and whatever their response is to
this group as well. That may spur others to do so similar requests.

It will be much
easier this way than individually mailing the above three.

I seriously doubt some public vote would be easier than directly
contacting a few companies. I also doubt that it would be effective.
The power of stating "company xyz's tool supports this feature" is
also a useful prod since it potentially is lost revenue then to a
competitor if they can't say they have the feature also.

just wondering,is it possible?

Sure...many things are possible.

KJ

 

[Andy]

The power of stating "company xyz's tool supports this feature" is
also a useful prod since it potentially is lost revenue then to a
competitor if they can't say they have the feature also.

This has always been my most effective means of getting a vendor to
support a language capability.

Andy

 

[HT-Lab]

I agree with KJ, as I wrote before, raising an SR (by maintenance paying
customers) is more effective than a petition since the only thing that counts is
$$$.

I just spoke to a Mentor engineer and there is some good, bad and worrying news.
The good news is that Modelsim 6.7 (expected around Xmas) will have additional
VHDL-2008 support including "case with don't cares", "simplified conditional
expression (if , ?(=,<,....)", "Array/Scalar Logic Operators" to name a few. The
bad news is that some constructs are not expected until 6.8 (2012?) such as
"generic types on packages" but the worrying one is that constructs like
"simplified case statements", "slices in array aggregates" and "conditional and
selected assignment in sequential code" have no release date at all.

Of course this is all subject to change!

So if you raise an SR you might want to ask for some of the none-release date
constructs

Hans
www.ht-lab.com

Is it possible to create some vote/public letter to convince Mentor,
Aldec and Synplicity.

That vote already occurred. The vote was when the standard was
approved. Mentor and other companies are represented on that public
forum and are participants in the standards development process.

The VHDL-2008 language develop team can start such a public voting so
that people can show that they want VHDL-2008 support.

Petitions are easy and in this case likely to be ineffective. Simply
contact Mentor (and others) directly through their support page and
request implementation of whatever VHDL-2008 features you need the
most and ask them when they're scheduling release of full VHDL-2008.
To gather public interest that might be similar to yours, simply take
whatever you've posted with Mentor and whatever their response is to
this group as well. That may spur others to do so similar requests.

It will be much
easier this way than individually mailing the above three.

I seriously doubt some public vote would be easier than directly
contacting a few companies. I also doubt that it would be effective.
The power of stating "company xyz's tool supports this feature" is
also a useful prod since it potentially is lost revenue then to a
competitor if they can't say they have the feature also.

just wondering,is it possible?

Sure...many things are possible.

KJ

 

[Tricky]

I think I got the same copy/paste reply, 5 mins after raising the
support request. It is all marked as a "tentative" release schedule:

Read out ports
Targeted release: 6.7
Simplified Case Statements
Targeted release: No target release at this time.
Case with don't care (-)
Targeted release: 6.7
Simplified conditional expression (if , ?(=,<,....)
Targeted release: 6.7
Expressions in port maps
Questa/ModelSim supports conv funcs, globally static expressions
in port maps today.
Targeted release: 6.7 (remaining functionality).
Conditional and Selected assignment in sequential code
Targeted release: Questa/ModelSim still investigating
Unary Reduction Operators
Partial support in Questa/ModelSim today. std_ulogic_vector is
not yet supported.
Targeted release: 6.7 (std_ulogic_vector).
Array/Scalar Logic Operators
Partial support in Questa/ModelSim today. std_ulogic_vector is
not yet supported.
Targeted release: 6.7 (std_ulogic_vector).
Slices in array aggregates
Targeted release: No target release at this time.
Source code encryption
Supported today in Questa/ModelSim.
Fixed Point Packages
Questa/ModelSim supports the non-generic version of the packages
in 6.5.
Targeted release: 6.8 (requires generic type capability).
generic type
Targeted release: 6.8.

 

[JerryNV]

... and that's how it looks in ALDEC tools

OK, since somebody posted Mentor list, half of my work was done . I have added [Supported in Riviera] tag where appropriate:
Read out ports [Supported in Riviera]
Targeted release: 6.7
Simplified Case Statements [Supported in Riviera]
Targeted release: No target release at this time.
Case with don't care (-) [Supported in Riviera]
Targeted release: 6.7
Simplified conditional expression (if , ?(=,<,....) [Supported in Riviera]
Targeted release: 6.7
Expressions in port maps [Supported in Riviera]
Questa/ModelSim supports conv funcs, globally static expressions
in port maps today.
Targeted release: 6.7 (remaining functionality).
Conditional and Selected assignment in sequential code [Supported in Riviera]
Targeted release: Questa/ModelSim still investigating
Unary Reduction Operators [Supported in Riviera]
Partial support in Questa/ModelSim today. std_ulogic_vector is
not yet supported.
Targeted release: 6.7 (std_ulogic_vector).
Array/Scalar Logic Operators [Supported in Riviera]
Partial support in Questa/ModelSim today. std_ulogic_vector is
not yet supported.
Targeted release: 6.7 (std_ulogic_vector).
Slices in array aggregates [Supported in Riviera]
Targeted release: No target release at this time.
Source code encryption [Supported in Riviera]
Supported today in Questa/ModelSim.
Fixed Point Packages [non-generic version supported in Riviera]
Questa/ModelSim supports the non-generic version of the packages
in 6.5.
Targeted release: 6.8 (requires generic type capability).
generic type [scheduled for 2011]
Targeted release: 6.8.
Other supported items:
- ‘else’ in ‘if..generate’
- ‘case..generate’
- process(all)
- absolute and relative external names (hierarchical paths to access non local objects)
- context declaration and context clause
- ENV package with STOP and FINISH
It seems that Riviera gets new features earlier than Active-HDL, so a few items listed as supported for Riviera may not work in Active-HDL.
Two major tasks remaining:
- generic types (this one turns both compiler and simulation kernel upside-down)
- allowing PSL in running code – now it is allowed in comments only (turns parser upside down)

 

[hssig]

Simply contact Mentor (and others) directly through their support page and
request implementation of whatever VHDL-2008 features you need

Here we go round in circles, I mean before I am not able to try a new
feature out I can whether assess it nor request it rationally. Or I
request all features and try them out afterwards.

Cheers,
hssig

 

[hssig]

Some additional info to Tricky's road map (from answer to my support
request) :

* Modelsim 6.8 will see full VHDL-2008 support
* Modelsim 6.7 will be available end of this year.
* Support of process(ALL) in ModelSim 6.7, maybe 6.8
* "The point is that one of the several essential factors that can
prioritize the implementation of such enhancement requests implies the
number of customers that requested these. That is why any feedback on
this matter is appreciated so we can continually improve the quality
of our releases."

Cheers,
Heinze

 

[Chris Higgs]

Some additional info to Tricky's road map (from answer to my support
request) :

* Modelsim 6.8 will see full VHDL-2008 support

Does "full VHDL-2008 support" include VHPI? Somehow, I doubt it.

 

[Chris Higgs]

Mentor for some strange reason thinks that their FLI "will work" for
this.   Personally I'd rather see a real PLI that is more standard.

VHPI is included in the VHDL-2008 standard and is now _the_ PLI
standard. For a vendor to claim full VHDL-2008 support but not
implement VHPI is a total misnomer.