Does VHDL accept floating point design in "RTL-like" designs?

[Mr. Ken]

I am testing out some idea which will be later converted to fixed point and
into Verilog RTL codes.

I would probably need some floating point arithmetic like multiplication,
cosine, sine, square root etc, but C is not good for data observation or bit
manipulation or sequence control.

Verilog doesn't allow registers/operations with REAL types to be used in
clock or edge statements.

Does VHDL allow this?

My idea of using floating point in RTL is only to test some ideas in
simulation,
not meant for synthesis.

 

[Mr. Ken]

I am testing out some idea which will be later converted to fixed point and
into Verilog RTL codes.

I would probably need some floating point arithmetic like multiplication,
cosine, sine, square root etc, but C is not good for data observation or bit
manipulation or sequence control.

Verilog doesn't allow registers/operations with REAL types to be used in
clock or edge statements.

Does VHDL allow this?

My idea of using floating point in RTL is only to test some ideas in
simulation,
not meant for synthesis.

I think the mathpack has all the arithmetic functions.
Remaining question is, can these functions used in edge triggered "as if" a
real
register in normal RTL design?

 

[Marcus Harnisch]

Verilog doesn't allow registers/operations with REAL types to be used in
clock or edge statements.

Could you please elaborate on this?

-- Marcus

 

[oussama.mlika]

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[Mr. Ken]

Could you please elaborate on this?

-- Marcus

For example, in my Verilog codes, I want to code everything like they
eventually appear
in fixed point design, only that it's in floating point and for simulation
only. (Avoid handling
bit-width etc for the time being).

My design will involve manipulation of 10-bit addresses, in HDL simulator I
can visualize
the waveforms and would be easier for me I guess.

I guess VHDL can do this, I tried for that.



// -------------------------------------------
module float_multiply;
(real) input data_a, data_b; // How to make real type ports in verilog?
(real) output data_c_out;

real wire data_c_out; // Real wire?
real reg data_c; // Real wire?

always @(posedge clock or negedge reset) begin // There will be error
message here in ModelSim
if (~reset)
data_c <= 0.0;
else begin
data_c <= data_a * data_b; etc.
end
end

assign data_c_out = data_c;

endmodule
// ------------------------------------------- //

 

[Marcus Harnisch]

Now that's a slightly different problem from what you initialy wrote.

The Verilog `real' type is similar to `integer'. It behaves like a
variable (as opposed to wire) but cannot be used as module port.

It can be used as task/function port, however.

I guess VHDL can do this, I tried for that.

Yes. But apart of the question which language you choose, I wonder if
you should do it that way at all. Conversion of the design (think of
all the intermediate signals' types) will be rather difficult.

Also consider that if you use VHDL, you will end up with two (lossy,
in the worst case) conversions of your design.

VHDL-real->VHDL-fixed->Verilog-fixed

I would choose a pessimistic (i.e. possibly higher than necessary)
range/precision, determine the bit-width and go from there. Only where
it comes to doing the math, I'd employ functions which use the
underlying type (perhaps real).

Another option would be to use the C-interface of your preferred
simulator and implement the conversion functions using libm which
would also give you the arithmetic stuff for free.

Regards,
-- Marcus

 

[Marcus Harnisch]

....the last option being, the Verilog system tasks $bitstoreal and
$realtobits which have been introduced as workaround for the lack of
`real' ports.

Regards,
-- Marcus

note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]

-- Michael McNamara
(http://www.veripool.com/verilog-mode_news.html)