DRAM controller???

[Kenneth]

Do anyone here have any idea of how to use VHDL to come out a design
for Dynamic RAM Controller?

I need some guidance. Thankz

 

[Martin Thompson]

Do anyone here have any idea of how to use VHDL to come out a design
for Dynamic RAM Controller?

I need some guidance. Thankz

Get some DRAM datasheets, look at the timing diagrams. Figure out
which transactions you will need for your application (you may not
need refresh, or burst transfers for example)

Repeat:
Pick a transaction type you want to work on
Draw a state machine
Code it
Simulate
make it work
Until done all the transactions you need.

Beyond that - if you have specific problems, post further...

Cheers,
Martin

 

[radarman]

Which DRAM are you targetting? There are several different kinds at the
moment. There is the ancient original DRAM chips - which I doubt you
can even buy anymore, then, you have the old FPM (fast page mode) and
EDO (extended data out) versions that run between 50 and 60 ns. Next is
SDR (single data rate) DRAM that starts operating at 100 MHz (10ns) and
lower. Newer versions include DDR (double data rate) and QDR (quad data
rate) that clock the data on both edges and on the edges and in the
middle respectively. There is also Rambus DRAM.

For the oldest DRAM parts, you will probably have to consult the data
sheet and write your own. For SDR DRAM, Altera has an RTL design that
should work - though licensing is limited to Altera parts. For DDR
DRAM, opencores.org has a nifty design that you could use whole, or as
inspiration for your own. QDR DRAM is still pretty new, so you will
either be consulting the datasheet, or coughing up cash for an IP core.

Each type has it's own unique properties and limitations - so you
really need to target some parts first.