VITAL needed for memories modeling ?

Discussion in 'VHDL' started by RealInfo, Apr 16, 2009.

  1. RealInfo

    RealInfo Guest

    Hi all

    I am learning now modeling of memories of all kinds , RAM , SRAM , DRAM etc
    My question is : Do I have to use VITAL in the memories models which are
    behavioral , not for synthesis , or it is ok to use
    the standard VHDL TIME generics to describe the true timing of a memory
    modeled with VHDL ?

    RealInfo, Apr 16, 2009
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