Edge Detection circuit.

[Raghavendra]

Hi all,
Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.
Regards
Raghavendra.Sortur

 

[Paul Uiterlinden]

Hi all,
Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.

By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These two
latches form a so called master-slave pair.

Google is your friend. See e.g.
http://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141_f03/Lectures/Lecture24-Sequential.pdf

Paul.

 

[Laurent Gauch]

By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These two
latches form a so called master-slave pair.

Google is your friend. See e.g.
http://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141_f03/Lectures/Lecture24-Sequential.pdf


Paul.

One Flip-flop is enough if your input signal is synchronous with the clock.

Best regards,
Laurent
www.amontec.com

 

[Guitarman]

Hi all,
Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.
Regards
Raghavendra.Sortur

Here is a Process that finds the rising edge of YOUR_SIG signal

-- This process is used to find the rising edge of the YOUR_SIG
Edge_find: process (CLK_IN,RESET_IN)
begin
if RESET_IN ='1' then -- Async Reset
YOUR_SIG_FILTER <= "00000000";
YOUR_SIG_EDGE <= '0';
elsif rising_edge (CLK_IN) then
-- Detects rising Edge of YOUR_SIG
if YOUR_SIG_FILTER = "11110000" then
YOUR_SIG_EDGE <= '1';
else
YOUR_SIG_EDGE <= '0';
end if;
--Shifts in new input values into filter
YOUR_SIG_FILTER(7 downto 0) <= YOUR_SIG & YOUR_SIG_FILTER(7 downto
1);
end if;
end process;

When YOUR_SIG_EDGE is '1' then you have a rising edge. I used the 8
bit registar as a filter. You wouldn't have to use the 8 bits a single
signal would work.

 

[rickman]

One Flip-flop is enough if your input signal is synchronous with the clock.

You are on a different topic.

--

Rick "rickman" Collins

(e-mail address removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Eric Smith]

Flip flop differs from a latch because of edge detection
circuit.How edge detection circuit is implemented.

By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These
two latches form a so called master-slave pair.

That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.

One of the earliest true edge-triggered D flip-flops was the SN7474.
There's a logic diagram at the bottom right of the first page of the
TI data sheet, which can be found here:
http://focus.ti.com/docs/prod/folders/print/sn7474.html

It's a little tricky to understand; it is helpful to redraw the
logic diagram with the asynchronous preset and clear inputs omitted.
I haven't found any good written description of how it works, but
there's probably one in a digital design textbook somewhere.

An example of an edge-triggered J-K/ flip-flop is the SN74109. There's
a logic diagram in its data sheet as well.

 

[rickman]

That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.

I'm not clear why you say it is "sensitive" to input changes in the low
clock period. The input can change many times while the clock is low,
but only the last state of the input before the clock rises will be
remembered by the first latch and therefore by the second latch which is
the output.

One of the earliest true edge-triggered D flip-flops was the SN7474.
There's a logic diagram at the bottom right of the first page of the
TI data sheet, which can be found here:
http://focus.ti.com/docs/prod/folders/print/sn7474.html

It's a little tricky to understand; it is helpful to redraw the
logic diagram with the asynchronous preset and clear inputs omitted.
I haven't found any good written description of how it works, but
there's probably one in a digital design textbook somewhere.

An example of an edge-triggered J-K/ flip-flop is the SN74109. There's
a logic diagram in its data sheet as well.

--

Rick "rickman" Collins

(e-mail address removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Ken Smith]

That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.

I think someone didn't read carefully before posting. The master/slave
flip flop does implement the edge triggered logic.

There's a logic diagram at the bottom right of the first page of the
TI data sheet, which can be found here:
http://focus.ti.com/docs/prod/folders/print/sn7474.html

The 7474 is a slightly tricky master-slave circuit. The tricky bit is
that the power connection of the master is driven by a transistor running
from the clock input. The master section is only powered as a flip-flop
when the clock is high. When the clcok is low, the base of one transistor
or the other is pulled low depending on the state of the D input.

 

[Ken Smith]

I'm not clear why you say it is "sensitive" to input changes in the low
clock period. The input can change many times while the clock is low,
but only the last state of the input before the clock rises will be
remembered by the first latch and therefore by the second latch which is
the output.

He just didn't read your post carefully. You are right about how it
works.

 

[Eric Smith]

By two latches in succesion, the first has an active low enable
(transparant while its enable is low), the second active high. These
two latches form a so called master-slave pair.

That's how the pulse-triggered flip-flops worked, but that technique has
not been in common use for a long time. It is not truly edge-sensitive,
because it is sensitive to input changes during the entire low period of
the clock, not just a narrow window near the rising edge.

I think someone didn't read carefully before posting. The master/slave
flip flop does implement the edge triggered logic.

Quoting from "The Art of Digital Design" by Prosser and Winkel,
Second Edition, Chapter 4:

The master-slave flip-flop appears to be an attractive edge-driven
device. Why are we not content with this design? Because the
master flip-flop is still a 1's catcher during the positive half
of the clock cycle. This means that R and S must stabilize during
the negative half of the clock, since the master flip-flop will
react to any T glitches during the positive clock phase. We could
greatly simplify our digital circuit designs if we could eliminate
the 1's-catching behavior. We need a flip-flop that samples its
inputs only on a clock edge and changes its outputs only as the
result of the clock edge. Such a device is called a <i>pure edge-
driven flip-flop</i>.

Unfortunately the authors do not explain the construction of such
a device, though the 7474 and 74109 are real-world examples of it.

Metastability is not explained until Chapter 12.

The 7474 is a slightly tricky master-slave circuit.

The 7474 is not a master-slave flip-flop. It actually contains three
S-R flip-flops in a non-obvious configuration, very much unlike what
Paul Uiterlinden described.

 

[Pieter Hulshoff]

Could we please all use the same terminology? A pulse (level) triggered
memory device is usually called a latch. An edge triggered memory device is
usually called a flip-flop.

Unfortunately the authors do not explain the construction of such
a device, though the 7474 and 74109 are real-world examples of it.

The idea of a FF that isn't partial to meta-stability is nice, but in
general not affordable within ASICs or FPGAs. That's why we have to be very
careful when signals cross clock boundaries.

The 7474 is not a master-slave flip-flop. It actually contains three
S-R flip-flops in a non-obvious configuration, very much unlike what
Paul Uiterlinden described.

I'm not familiar with the 7474, but I know that constructions with 3 latches
in sequence are sometimes used when transferring signals over a larger
distance. It creates, in some situations, a better clock data relation at
the receiving FF.

Regards,
Pieter Hulshoff

 

[Mike Treseler]

I'm not clear why you say it is "sensitive" to input changes in the low
clock period. The input can change many times while the clock is low,
but only the last state of the input before the clock rises will be
remembered by the first latch and therefore by the second latch which is
the output.

I agree. The master latch(mux) is enabled by the constant clock.
The data setup requirement is to the rising edge, where
the slave latch(mux) is enabled. This is exactly how the
Actel ACT1 devices made D-flops.

-- Mike Treseler

 

[Mike Treseler]

Quoting from "The Art of Digital Design" by Prosser and Winkel,
Second Edition, Chapter 4:

The master-slave flip-flop appears to be an attractive edge-driven
device. Why are we not content with this design? Because the
master flip-flop is still a 1's catcher during the positive half
of the clock cycle.

They are either talking about a different circuit, or they
got it wrong. The master latch(mux) follows the D input
input, but the only "catching" behavior is at the rising
clock edge when the master data passes to the slave latch(mux).

-- Mike Treseler

 

[Eric Smith]

Could we please all use the same terminology? A pulse (level) triggered
memory device is usually called a latch. An edge triggered memory device is
usually called a flip-flop.

The book I was quoting distinguishes between level-triggered (latch),
pulse-triggered (master-slave), and edge-triggered. Sorry, I don't know
what better terminology to use to describe it.

The point was that the behavior of a master-slave FF is NOT always
the same as that of an edge-triggered FF. This is why master-slave FFs
went out of style in the late 1970s.

The idea of a FF that isn't partial to meta-stability is nice, but in

That's not what they're talking about, and it's not even theoretically
possible to eliminate metastability.

I'm not familiar with the 7474, but I know that constructions with 3 latches
in sequence are sometimes used when transferring signals over a larger
distance. It creates, in some situations, a better clock data relation at
the receiving FF.

The 7474 does NOT have three in sequence. It has two SR flops in the
first stage, and one in the second. There's no easy way to explain it,
which is why I referenced the diagram in the TI data sheet.

 

[Pieter Hulshoff]

The book I was quoting distinguishes between level-triggered (latch),
pulse-triggered (master-slave), and edge-triggered. Sorry, I don't know
what better terminology to use to describe it.

It seems I could have used a bit of reading up on my knowledge as well.
Might be a language thing too (I'm Dutch. It appears in literature a
difference is made between level sensitive (Latch), and level triggered
(AKA pulse triggered). There are indeed two different types of FFs: pulse
triggered and edge triggered.

The point was that the behavior of a master-slave FF is NOT always
the same as that of an edge-triggered FF. This is why master-slave FFs
went out of style in the late 1970s.

From what I could find, and it can also be found in the lecture Paul
Uiterlinden wrote about, it's the pulse triggered FF that has the problem
you described, and AFAIK the pulse triggered FF that went out of style.
This is also what I believe Mike Treseler said in a previous post.

That's not what they're talking about, and it's not even theoretically
possible to eliminate metastability.

True, but it's possible to create circuits that properly take signals from
one clock area to the next, despite metastability.

The 7474 does NOT have three in sequence. It has two SR flops in the
first stage, and one in the second. There's no easy way to explain it,
which is why I referenced the diagram in the TI data sheet.

I just had a look at the datasheet (my apologies for not doing so before
posting). From what I can tell that device contains 2 FFs, each edge
triggered, and each having an asynchronous set and reset. The asynchronous
set/reset is why they need 3 latches i.s.o. 2.

Regards,

Pieter Hulshoff

 

[Ken Smith]

device. Why are we not content with this design? Because the
master flip-flop is still a 1's catcher during the positive half
of the clock cycle. This means that R and S must stabilize during
the negative half of the clock, since the master flip-flop will
react to any T glitches during the positive clock phase.

They are either (a) speaking of a different cicruit than the common
master-slave flip-flip or (b) wrong.

If you want to see a schematic that is easier to understand, look at the
CD4013's data sheet. It is much less tricky in how things are done.

The master section of the master-slave circuit followes its input when the
clock is low. Its output drives the input of the slave section. The
slave section follows its input when the clock is high. Whatever state
the master section is in, will appear at the output just after the rising
edge of the clock and remain there until the next rising edge of the
clock.

Unfortunately the authors do not explain the construction of such
a device, though the 7474 and 74109 are real-world examples of it.

Take a very careful look at the 7474's schematic. You will discover that
it is just a funny sort of master-slave design.

Metastability is not explained until Chapter 12.


The 7474 is not a master-slave flip-flop. It actually contains three
S-R flip-flops in a non-obvious configuration, very much unlike what
Paul Uiterlinden described.

I'm looking at the transistor level schematic of the 7474. There are two
and only 2 flip-flops in the transistor level schematic. Its in the data
sheet. Take a look. There are a cross coupled pair near the bottom of
the page forming the master and a more complex slave above it.

If you look at the "logic diagram" you will see that the uppermost
flip-flip takes the PRE/ and CLR/ as inputs. In the transistor schematic
that part is replaced by some simple stearing logic that does not involve
feedback.

 

[Ken Smith]

Could we please all use the same terminology? A pulse (level) triggered
memory device is usually called a latch. An edge triggered memory device is
usually called a flip-flop.

I'm using:

In the following, you can exchange "high" with "low" and get the neg.
polarity version.

The "D" input is the data input to the flip-flip

"edge-triggered" means that the output takes on the logic value that was
at the "D" input when the clock went from low to high and remains that way
until the next time the clock goes from low to high.


"pulse" "level triggered" and "latch" all refer to circuits where the
output either (a) follows the input or (b) is not useful while the clock
is high and holds the value when the clock is low. In most cases, the
output follows the input but the (b) case can also be true.

I'm not familiar with the 7474, but I know that constructions with 3 latches
in sequence are sometimes used when transferring signals over a larger
distance. It creates, in some situations, a better clock data relation at
the receiving FF.

The 3rd flip-flop in the "logic diagram" handles stearing of the PRE/ and
CLR/ signals it is in parallel with the main master/slave pair.

When dealing with signals coming in from the outside, it is common to put
a couple or 3 flip-flops in the path with a bit of logic around them.
These circuits, lower the odds of a glitch at the output at the cost of a
delay to the input signal. A M.S. state on the first stage has to remain
for a whole clock cycle to cause trouble. The odds of that are quite low.

 

[digitalpbk]

Edge Detection Project

Image Edges can be detected using FPGA project (edge.kitiyo.com)

Edges on signals can be detected using a high pass RC circuit.