Error please Help

Discussion in 'VHDL' started by Isaac, Aug 13, 2003.

  1. Isaac

    Isaac Guest

    Hi Mates I am getting following errors when I start simulating my

    Delta count overflow - stopped. Try to increase the iterations limit
    in simulator preferences.
    # Fatal error occurred during simulation.

    How to remove this error ?

    Thanking you in advance .

    Isaac, Aug 13, 2003
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  2. Isaac

    Jim Wu Guest

    If you're using ModelSim, you can change the iteration limit from the
    Simuluation Options window. You can also change it in modelsim.ini file.

    Jim Wu
    Jim Wu, Aug 13, 2003
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  3. Isaac

    Ian Poole Guest

    This is usually caused by an error in the original VHDL that results in an
    infinite loop which consumes zero simulation time. Raising the maximum delta
    limit is fairly pointless, since you probably have an infinite loop...

    The usual error is a process with neither a sensitivity list nor a wait
    statement eg:
    if (Reset = '1') then
    sig <= '0';
    elsif (Rising_edge(Clk)) then
    sig <= D;
    end if;
    end process;

    Processes with feedback can cause errors. Try this concurrent statement and
    see what happens!:
    sig <= not sig;

    Alternatively, you may have a process with wait statments inside a while
    loop/if statement etc that means the wait is bypassed for some reason eg:

    if (Ready = '1') then
    -- do something
    wait for 10 ns;
    end if;
    end process;

    What happens to this process if Ready /= '1' ???

    Also test bench processes which are supposed to run only once and terminate,
    but have a missing wait; at the end. This particular example won't give a
    delta limit error, but illustrates what I mean:
    A <= "000";
    wait for 10 ns;
    A <= "010";
    wait for 10 ns;
    A <= "100";
    -- wait; -- this effectively stops this process
    end process;


    Ian Poole, Aug 13, 2003
  4. The given process will never stop executing but it will NOT generate the
    delta count overflow.
    (In the example the tool probably raised a warning missing wait statement
    during compilation/analyzing).

    A simple example that generates delta count is the following CONCURRENT
    y <= NOT y;

    In general increasing the upper limit of the delta count will not help.
    Check the
    VHDL description. If you can not find the 'loop' it maybe possible to
    perform a
    step by step simulation (in combination with a break), depending on your
    simulation environment.

    Egbert Molenkamp
    Egbert Molenkamp, Aug 13, 2003
  5. Isaac

    Jim Wu Guest

    For Modelsim, even a not very big loop would cause the problem as the
    default limit is 5000.

    Jim Wu
    Jim Wu, Aug 13, 2003
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