for loop and processes simple problem

[pupillo]

Hi,
here below a stupid code to show a problem that I can't understand.
I have a 8 bit register (myReg) and a clk.
On each rising edge of clk a process should set myReg(0 to 1) to '0' using a for loop and another process (always on each ris. edge) set the other bits to '0' as well .
When I simulate (tried more simulators) I get zeroes on myReg(0 to 1) (ok) but U on the others (2 to 7). WHY?

If I don't use the for loop (and I simply use assignments) it works.
If I move the assignments done by the second process, after the end loop line of the first process it works.
Thnaks
Pupillo



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity user_logic is
end entity user_logic;

architecture myArch of user_logic is

signal myReg : std_logic_vector(0 to 7);
signal myClk :std_logic;

begin

REG_0_1_WRITE_PROC : process( myClk ) is
begin
if myClk'event and myClk = '1' then
for index in 0 to 1 loop
myReg(index)<='0';
end loop;
end if;
end process REG_0_1_WRITE_PROC;


REG_2_7_WRITE_PROC : process( myClk ) is
begin

if myClk'event and myClk = '1' then
myReg(2 to 7) <= (others => '0');
end if;
end process REG_2_7_WRITE_PROC;


gen_clkrocess begin
while (true) loop
myClk<='0';
wait for 5 ns;
myClk<='1';
wait for 5 ns;
end loop;
end process;


end myArch;

 

[sridar]

Re:

You are missing a basic point. Signal Myreg is always assigned with the data "11000000" irrespective of any change in input signal. so simply use the assignment statement.

Process (clk)

begin

if rising_edge (clk) then

MyReg <= "11000000";

end if;

end process;

 

[pupillo]

Hi,
I know that there is always that assignment, but this stupid code is just for showing the problem
thanks