FPGA Camp is tomorrow - 11/11 - silicon valley - Dinner provided

Discussion in 'VHDL' started by Vikram, Nov 10, 2009.

  1. Vikram

    Vikram Guest

    To register visit http://www.fpgacentral.com/fpgacamp & yes DINNER
    will be provided so bring a friend !!

    There are two distinct phases in bringing an FPGA system to market:
    the design phase and the debug and verification phase. The primary
    tasks in the design phase are entry, simulation, and implementation.
    The primary tasks in the Debug and Verification phase are to validate
    the design and correct any bugs found.

    The recent advancements in FPGA densities have changed the way we
    think of design & debug of a FPGA. This camp will focus on what can
    you do as an engineer to make debugging your FPGA a science rather
    then an art. It will also introduce to you various tools that you can
    use to shorten the debug cycle.

    5:00 PM- 6:00 PM: Registration, Dinner & exhibits (booths from various
    6:00 PM - 6:05 PM: Introductions - Vikash Rungta
    6:05 PM - 8:30 PM: Tech Talk
    8:30 PM- 9:00 PM: Networking and exhibits (booths from various

    Tech talk from:
    * Eric Bogatin, BeTheSignal.com - How the board will screw up your
    beautiful transceiver signals, and what you can do about it
    * Sid Khattar, eInfoChip - Design and Validation Techniques for FPGA
    * Chris Schalick, Gaterocket - Debugging FPGA designs may be harder
    than you expect
    * Mike Peattie & Vinay Singh, Xilinx - Improving Productivity in FPGA
    Debug and Verification
    * Richard Wilson, Altium - Using FPGAs to embed test instruments into
    your PCB design
    * Gordon Getty, Agilent - Using Logic Analyzers, Scopes and other
    tools to debug your FPGA

    Registration: FREE! Feel free to bring a friend. Use the form below
    Or RSVP at linked in at http://events.linkedin.com/FPGACamp-Debugging-FPGA/pub/136177
    Vikram, Nov 10, 2009
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