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frequency divider by 2,3 with duty cycle 50%
pls anyone can help me verilog code for frequency divider by 2,3 with duty cycle 50%~~~ thx a lot
following verilog code is just for 2,4. I don't know how to do for frequency divider by 3. PLs help me~~ thx again
module freqdiv(q,Clk,Reset,i);
input Clk,Reset;
output q;
output i;
reg i;
reg q;
always @(posedge Reset or posedge Clk)
begin
if(Reset)
begin
q= 0;
i = 0;
end
else
begin
i =(q==1)? ~i : i ;
q = q +1;
end
end
endmodule
pls anyone can help me verilog code for frequency divider by 2,3 with duty cycle 50%~~~ thx a lot
following verilog code is just for 2,4. I don't know how to do for frequency divider by 3. PLs help me~~ thx again
module freqdiv(q,Clk,Reset,i);
input Clk,Reset;
output q;
output i;
reg i;
reg q;
always @(posedge Reset or posedge Clk)
begin
if(Reset)
begin
q= 0;
i = 0;
end
else
begin
i =(q==1)? ~i : i ;
q = q +1;
end
end
endmodule
Last edited: