I need a Verilog behavioral model (verilog behavioral code) for: - unsigned 8-bit division The module I have to use is this one: module divider( output reg[7:0] q, output reg[7:0] r, input [7:0] a,b); endmodule where a=b*q+r Is preferable to use SRT, Newton-Raphson or Goldschmidt algorithms to solve it. Can someone help me?