FPGA for Frequency Divider


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Mar 28, 2016
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Hello,

I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? Here I attach my code.

Thanks.
 

Attachments

  • Frequency Divider.txt
    1 KB · Views: 401
  • FreqDivider_tb.txt
    2.5 KB · Views: 386
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