FPGA for Frequency Divider

Discussion in 'VHDL' started by _Jaiko007, Mar 28, 2016.

  1. _Jaiko007

    _Jaiko007

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    Hello,

    I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? Here I attach my code.

    Thanks.
     

    Attached Files:

    _Jaiko007, Mar 28, 2016
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