"Global Variables" for configuration in VHDL

[Andy]

I would have preferred a solution with a kind of "shared variable",
but this seems not to work!?
Thanks
Peter

Do you want a solution, or do you want to use shared variables? Pick
one.

Andy

 

[Weng Tianxiang]

Because every time you call NextAddress, it changes the address. So
You would have to get lucky for the incoming address to match in the
ever changing match. Setting it to a constant means it never changes.




Asserts can be placed almost anywhere. for what you want, just put it
inside the architecture.
Try this:
assert false report my_ent'PATH_NAME & ": Address of something = " &
integer'image(ConstantAddress) severity NOTE;

Now, as discussed previously in another thread, asserts get treated
different by different synthesisors. I Know Quartus handles them very
well, but other synthesisors either ignore them or mishandle them and
just print Failures/errors as warnings!

"Direct use of the function "NextAddress" in the comparator gives no
syntax error it simply does not work!!?? "

It really works, but in a different way from your expecting respect.

You use "ModuleAddress" function in order to set a constant which is
called during synthesization.

Your "ModuleAddress" function in comparator is called when it is used
in implementation.

You didn't test to see "ModuleAddress" function in implementation.

Your method really gives a good example on how to use shared variable
and impure function
and the method has universal application meanings.

Thank you.

Weng

 

[pvwa]

"Direct use of the function "NextAddress" in the comparator gives no
syntax error it simply does not work!!?? "

It really works, but in a different way from your expecting respect.

You use "ModuleAddress" function in order to set a constant which is
called during synthesization.

This would have been what i wanted!
But even here, when i look at the RTL Schematic, i still see the adder
from the impure function!
It seems the synthesis does NOT really use it as a constant!!!???

Your "ModuleAddress" function in comparator is called when it is used
in implementation.

As hardware function!?

You didn't test to see "ModuleAddress" function in implementation.

And this is where i am stuck now!
Simulation did work as expected!

But the implementation (Xilinx ISE 9.1) does not! :-(
I tried my actual code (which is quite large) and it produces a lot of
strange errors already in synthesis!

Also my test code (see above) does synthesize but not map:

Running related packing...
ERRORack:198 - NCD was not produced. All logic was removed from
design. This
is usually due to having no input or output PAD connections in the
design and
no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE'
attributes to the design, or run 'map -u' to disable logic trimming
in the
mapper.

And this has something to do with the sharing variable construct.
Because when i replace this constant "pos" with simply a "real"
constant (3):

y <= '1' when Conv_integer(x)=3 else '0';

it implements!

Now your turn!

Peter (frustrated!)

 

[Martin Thompson]

Try this:
assert false report my_ent'PATH_NAME & ": Address of something = " &
integer'image(ConstantAddress) severity NOTE;

or just:

report my_ent'PATH_NAME & ": Address of something = " & etc....

Cheers,
Martin

 

[Tricky]

This would have been what i wanted!
But even here, when i look at the RTL Schematic, i still see the adder
from the impure function!
It seems the synthesis does NOT really use it as a constant!!!???

That because it is NOT constant.
the line of code you had:

y <= '1' when Conv_integer(x)=NextAddress else '0';

is really a process that looks like this:

process(x)
begin
if Conv_integer(x) = NextAddress then
y <= '1';
else
y <= '0';
end;
end process;

Because of this, next address is called every time x changes. Meaning
that the address incremenets for every change on X. Hence why XST put
an adder into the circuit.

 

[KJ]

This is really the main point!
My code is still in work and constantly changing. This is meant by
"removing"! I really want to be able to remove/substitute/add modules
in the source code without having to change too much in other parts
(functions)!

In that case you should switch tools. Stop using simulation and
synthesis tools and start using a word processor to create a
specification instead. It's much easier to manipulate addresses,
ports, bit fields, structures and functional descriptions in words and
diagrams first. Then you start coding...to that specification.

As far as i understand, you put the task of address generation into
the generation of constant vectors, which are then finally used!

That's the point...create the constants as constants, not variables.

These
vectors have to be linked "manually", by using the next proper start
adresses (range.right) as paramter in "Create_Addresses()". The task
of linking the addresses remains (the crucial problem!).

It's only a 'problem' because of your methodology which which seems to
be neither 'top/down' nor 'bottom/up'. At the start of this thread, I
assumed that you had your basic design structure and were looking for
a way to configure modules and address spaces that might (or might
not) be included in a particular instance of some more general and
somewhat stable design. But it seems that is not the case at all,
you're in the initial design creation stage and haven't taken the time
to simply write down what you intend the design to do.

Addresses of modules are rarely 'fluid', they are not something that
change from run to run, for the simple reason that most of the times
those addresses become interfaces to some other design that is outside
of the control of your synthesis tool (i.e. some software person who
controls the device). Those people will need hard fixed addresses,
bit definitions and such that don't change simply because you decide
to reorder modules within a text file in your code.

If you instead give a go at working all of these issues out where it
is much easier to make big changes (i.e. in your specification for
your design in words and figures) life will be much easier.

And again, if
i have to change my code i have to be very careful to reestablish the
linking!

Actually if you have the overall architecture of your design worked
out, you'll find that you won't need any of this manual linking and
your whole purpose for starging this thread will become moot.

Again, I thought there is a much simpler solution (something like
"impure functions" see below!)

The simplest solution is to first write a specification
document...THEN start writing code to that specification.

Not only will that document come in handy for yourself when it comes
to coding and verifying the design but it will be useful to others who
will have to write code to control your device. Even if that 'other'
person is actually 'you' writing code, you'll find that document comes
in handy because you have a completely different perspective when
you're writing code to control something than you had when you were
writing code to create that exact same something. The same difference
of perspective occurs when it comes to writing a testbench to control
and test something you designed yourself. It's the difference between
looking in at a design versus looking out from a design...it really is
a totally different viewpoint.

But your proposal (in contrary to mine) is interesting anyway! Maybe
it simplifies overall editing of my code! Give me some time and i will
give it a try!

Actually my proposal (and the whole other sub-thread having to do with
shared variables) are probably both very poor paths for you to go down
at this point. They are more relevant in the context of some more
general (and relatively stable) overall design that you are trying to
create specific design instances that include or don't include
modules, or the number of modules of a particular type is a design
parameter. In that context, the method I outlined is probably the
best and simplest way since it is explicitly calculating constants
that are in fact constants. Using shared variables to create
constants is...well...unusual.

Kevin Jennings

 

[pvwa]

Hi Tricky!

That because it is NOT constant.
the line of code you had:

y <= '1' when Conv_integer(x)=NextAddress else '0';

is really a process that looks like this:

process(x)
begin
  if Conv_integer(x) = NextAddress then
    y <= '1';
  else
    y <= '0';
  end;
end process;

Because of this, next address is called every time x changes. Meaning
that the address incremenets for every change on X. Hence why XST put
an adder into the circuit.

Yes, i understand this, but as i said, i used this code:

architecture Behavioral of MyModule is
constant ModuleAddress: integer := NextAddress;
begin
y <= '1' when Conv_integer(x)=ModuleAddress else '0';
end Behavioral;

So, i first generate the constant ModuleAddress, which seems to work
fine in the Simulator, but fails in the implementation!

Peter

 

[Tricky]

Hi Tricky!








Yes, i understand this, but as i said, i used this code:

architecture Behavioral of MyModule is
        constant ModuleAddress: integer := NextAddress;
begin
        y <= '1' when Conv_integer(x)=ModuleAddress else '0';
end Behavioral;

So, i first generate the constant ModuleAddress, which seems to work
fine in the Simulator, but fails in the implementation!

Peter

It could be that the synthesisor doesnt like what you're doing with
shared variables, as it isnt exactly a normal way to go about things.
Find out what ModuleAddress has been set to in the implementation, and
maybe raise and enhancement request.