half period pulse

Discussion in 'VHDL' started by john, Mar 20, 2008.

  1. john

    john Guest

    Hello,

    I need to genearte a pulse for half of the clock cycle. for example if
    clock = '1' then pulse= '1', if clock ='0' then pulse ='0'. So, I do
    not want the pulse to be high for one clock period but only for half
    of the clock period. I want to load the data into the buffer using
    this pulse.

    Regards,
    John
     
    john, Mar 20, 2008
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  2. john

    jeppe

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    From the description you give could you just use clock signal directly ;-)

    Have you consider using both rising and falling edge of the clock signal?

    If your using a DCM will it be possible the double the clock frequency and get the pulse your asking for.

    Your welcome
    Jeppe
     
    Last edited: Mar 20, 2008
    jeppe, Mar 20, 2008
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  3. First generate a single pulse, synchronous to the clock.
    Then OR (or AND, according to taste on polarity) that pulse with the
    original clock.
    If your original "single pulse" runs for several clocks, this tactic
    will give you a burst of clock pulses.
    Some old TTL chips (74166) had the OR gate on-chip, to support this kind
    of device.
     
    David R Brooks, Mar 21, 2008
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