Small problem in VHDL

[zhe]

Hi friends,

I'm new here and I meet a problem in VHDL, Could anybody please help me out?

The module I need

entity transfer is
Port ( input : in STD_LOGIC_VECTOR (1 downto 0);
clk : in STD_LOGIC;
output : out STD_LOGIC);
end transfer;

architecture Behavioral of transfer is
begin

here if input is "01",output should be a 2 clock cycle long pulse
if input is "10", output should be a 4 clock cycle long pulse
if input is "11", output should be a 6 clock cycle long pulse
if input is "00", ouput remain low.

need sychronized sythesisable circuit...
input ONLY LAST ONE clock cycle

end Behavioral;


thanks!

 

[jeppe]

A solution

bHi
First - I believe you learn more by doing your homework yourself - but nevermind

The most traditional solution to this problem would be a statemachine with say 13 state (one idle and 2+4+6)

This solution however based on a counter and variables.

--------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pulse_generator1 is
	Port ( input : in  STD_LOGIC_VECTOR (1 downto 0);
				clk : in  STD_LOGIC;
			output : out  STD_LOGIC);
end pulse_generator1;

architecture Behavioral of pulse_generator1 is

begin

	process( Clk)
		type		states is (Idle, Pulse);
		variable state: states := Idle;
		variable counter: std_logic_vector( 2 downto 0);
	begin
		if rising_edge( clk) then
			case state is
				when Idle  =>
						if input /= "00" then
							state   := Pulse;
							counter := input&'0'; -- Counter = input*2
						end if;
						output <= '0';
				when Pulse =>
						if counter > "001" then
							counter := counter-1;
						else
							counter := "000";
							state   := Idle;
						end if;
						output <= '1';
			end case;
		end if;
	end process;

end Behavioral;

 

[zhe]

Jeppe, thank you so much. actrually it is from a part of my project assignment. I don't know why but I just suddenly stuck at here for a few hours! I had thought about using counter but just cannot make it done. Maybe next time I should post my wrong code and you can point out my weakness in solving this kind of problem. Again, thanks for your self-explaining code.