Help in VHDL for Test becnh signal generation

[sdon]

Hello friends hi..

i have two signal say a and b, here a is period signal having period of 3.3 ms and i want to generate signal b in such a manner that during high time of signal a,signal b should in "X" and remain till 399 ns after signal a goes low and then signal b start generating in period of 1024 ns as follow

signal in state "X" uptill 532 ns
signal in state "U" uptill 80 ms
signal in state "1" uptill 186 ms
signal in state "U" uptill 80 ms
signal in state "1" uptill 186 ms

so plz me guys out of this

thanx in advance to all...........

 

[thecolororange]

If I'm understanding your question correctly, you could try something like the following:

signal first_time : std_logic := '0';

...

signal_a_process : process
begin
signal_a <= '1';
wait for 1650ns;
signal_a <= '0';
wait for 1650ns;
end process signal_a_process;

signal_b_process : process
begin
if first_time = '0' then
signal_b <= 'X';
wait for 2049ns;
first_time = '1';
end if;
signal_b <= 'X';
wait for 532ns;
signal_b <= 'U';
wait for 80ns;
-- and so on
end process signal_b_process;

Assuming you've named your signals "signal_a" and "signal_b", of course.