Definition Multiply and Division in VHDL

Discussion in 'VHDL' started by Adnan86, Apr 4, 2013.

  1. Adnan86


    Apr 4, 2013
    Likes Received:
    Hi ,
    I want execute this line in vhdl and i have no error but after compile it with Orcad and define the signal .. after RUN i have this error : Run time error accure at time 0 ns :
    a , b, is real array matrix ,
    c,d just real

    a(0,0) <= b(0,0) * (c/d)
    and if you have any idea for improve it , plz tell tanks

    plz help :stupido3:
    Last edited: Apr 4, 2013
    Adnan86, Apr 4, 2013
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