How in VHDL do I concatenate a bit many times?

[G Iveco]

In Verilog when I expand a signed value by 10 bits, I can use
data1 <= {{10{data[9]}}, data};

Does VHDL have the same neat tricks?

 

[Uncle Noah]

In Verilog when I expand a signed value by 10 bits, I can use
data1 <= {{10{data[9]}}, data};

Does VHDL have the same neat tricks?

The "others" and range specification constructs are your friend.

Let's say data is 10-bits and you want to perform sign-extension by 10
more bits.

data1 <= (19 downto 10 => data(9)) & data(9 downto 0);
or simply
data1 <= (19 downto 10 => data(9)) & data;

There are also other ways that will map to the same hardware given the
synthesis tool is able to elaborate to equivalent IR description.

Verilog is so crappy, maybe you are in ASIC business. I can't find any
other reason to keep working with Verilog (did that for a small period
of time: 1998-2000).

kavi

 

[G Iveco]

In Verilog when I expand a signed value by 10 bits, I can use
data1 <= {{10{data[9]}}, data};

Does VHDL have the same neat tricks?

The "others" and range specification constructs are your friend.

Let's say data is 10-bits and you want to perform sign-extension by 10
more bits.

data1 <= (19 downto 10 => data(9)) & data(9 downto 0);
or simply
data1 <= (19 downto 10 => data(9)) & data;

There are also other ways that will map to the same hardware given the
synthesis tool is able to elaborate to equivalent IR description.

Verilog is so crappy, maybe you are in ASIC business. I can't find any
other reason to keep working with Verilog (did that for a small period
of time: 1998-2000).

kavi

Thank you kavi for the trick.
I started with Verilog and felt it's easier to learn than VHDL..

 

[Jonathan Bromley]

In Verilog when I expand a signed value by 10 bits, I can use
data1 <= {{10{data[9]}}, data};

Does VHDL have the same neat tricks?

For the most part, VHDL lacks "neat tricks" and prefers
instead to be a consistent programming language

If you want to sign-extend a signed numeric value, then
please consider using the numeric_std package, creating
signals and variables of type "signed", and then
using the RESIZE function if you really need it (although
in most cases you won't, because the arithmetic bit width
rules are a lot simpler and more regular than Verilog's).

However, taking your question at face value:

As well as the "aggregate" suggestion you've already
seen, you could consider writing a function to mimic
Verilog's {N{}} replication operator:

function repeat(N: natural; B: std_logic)
return std_logic_vector
is
variable result: std_logic_vector(1 to N);
begin
for i in 1 to N loop
result(i) := B;
end loop;
return result;
end;

Now that you have the function, you can do stuff like

some_signal <= repeat(12, '1');

which is probably more natural for someone used to Verilog.

There are plenty of other ways that the function could have
generated its result. For example, it could have used the
"aggregate" formulation that you've already been shown:

return (1 to N => B);

But the 'for' loop is probably easier to understand, and
it also hints at how to write a second, overloaded
version of the function to do replication on a vector:

function repeat(N: natural; V: std_logic_vector)
return std_logic_vector is
constant L: natural := V'length;
variable result: std_logic_vector(0 to N*L - 1);
begin
for i in 0 to N-1 loop
result(i*L to i*L + L - 1) := V;
end loop;
return result;
end;

And now you can use "repeat" on either a std_logic bit,
or any std_logic_vector expression:

vec1 := repeat(4, '1'); --- "1111"
vec2 := repeat(2, vec1 & '0'); --- "1111011110"

Oh, and your sign extension:

target :=
repeat(target'length-source'length, source(source'left))
& source;

Oooh look, it's completely general.... no magic numbers.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Verilog is like a magic show with lots of
clever tricks - but you need to be an initiate to
see how to do most of those tricks really well.

VHDL is like a magic show where not only are all
the instructions for the tricks clearly printed
in the souvenir programme, but you're encouraged
to create your own tricks. Not good for those who
like to maintain an aura of mystery around their
work, but excellent for those of us who prefer
to be in control of what we're doing.

I've just finished teaching Verilog and SystemVerilog
to a bunch of very smart VHDL designers, whose
reaction generally was "I can see the point of
SystemVerilog for verification, but whoever would use
Verilog for RTL design when VHDL has been so much
better for so many years?". (Actually they said the
same thing using rather more colourful language, but
professional neutrality and personal probity suggest
I should not repeat the details.)
--
Jonathan Bromley, Consultant

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