Inout questions in testbench

[faust861]

Hi to all
after doing a certain number of exercizes, about a PWM and an Encoder, I'm doing the first example of a simple PLD. In this example, I use two bus from a DSP: an address bus, and a data bus.
The address bus permits, thanks to 2 encoders, to tell the PLD what functionality or module to be active.
The data bus gives and receives data to and from this modules.

The problem I can't solve is this. The data bus has to be bidirectional, so inout type.
My aim is this: when write signals for PWM arrive, this bus has to be read, while when read signal for Encoder arrives the bus has to be write.
This is the code I have written:

             dat_A <= dat_dsp(13 downto 0) when wr_pwmA = '1' else dat_dsp_reg(13 downto 0);
	dat_B <= dat_dsp(13 downto 0) when wr_pwmB = '1' else dat_dsp_reg(13 downto 0);
	dat_C <= dat_dsp(13 downto 0) when wr_pwmC = '1' else dat_dsp_reg(13 downto 0);
	dat_rit <= dat_dsp(14 downto 0) when rit_pwm = '1' else dat_dsp_reg(14 downto 0);
	
	uscita_bus_dati : process(rd_enc1,rd_enc2)
	begin
		if rd_enc1 = '1' then
			dat_dsp <= 	out_enc1;
		elsif rd_enc2 = '1' then
			dat_dsp <= out_enc2;
		else
			dat_dsp <= (others => 'Z');
		end if;
	end process;

where:
- dat_A, dat_B and so on are data to be given to the PWM
- wr_pwmA and so on are abilitation write signals
- rd_enc1 and rd_enc2 are abilitation read signals
- dat_dsp is the bidirectional port
The first part is about dat_dsp used as input, the second as output.

After this, I tried a testbench. I wanted to simulate this behaviour:
I send on dat_dsp the input for PWM, after I enable the Encoder and, after a certain time, I want to read it, so sending the reading on dat_dsp.
I wrote this:

dato_PWM : process
	begin
		tdat_dsp <= "00000000000000000000001110000100";
		wait;
end process;

where I force dat_dsp (tdat_dsp is the name in the testbench) at this value at the beginning to make work PWM.
Now the problem is that i think that it works, but Modelsim thinks that I force dat_dsp on this values as I would do with an output so I would see errors in the functionality of the circuit.
So, when it would have to write on data bus, the result is a vector where there are some X for the bits of the encoder exit different from the value I have forced at the beginning!

Is there any other mode, maybe righter, to tell a testbench that I want only to use that value as a signal, instead of force it for all the simulation time?

Thanks and sorry for the very long question