Instatiating Xilinx RAMs without using core generator wrappers

[Frank A. Kingswood]

Hallo!

[This might be a good question for BJ, can you beat him to it?]

I would like to instantiate some Xilinx technology specific RAMs
without using the core generator wrappers. My RAM block has generics
on it to specify the size, and I would like to pass these generics
into a XilinxCoreLib component.

There are 22 blkmemsp*.vhd files. Is there a Xilinx-recommended component
to instantiate?

Frank

 

[KJ]

Hallo!

[This might be a good question for BJ, can you beat him to it?]

I would like to instantiate some Xilinx technology specific RAMs
without using the core generator wrappers. My RAM block has generics
on it to specify the size, and I would like to pass these generics
into a XilinxCoreLib component.

Usually what I do in this type of situation is let the wizard produce
their files and then hand edit the file(s) as required to add the
generics that I want to the entity that they created and then use those
generics in place of where the wizard put my numbers in.

KJ

 

[manu]

Hello
apart from certain tricky cases in which you want to optimize internal
RAM usage by hand, RAM inference should be preferred to instantiation.
If you use RAM inference instead, you can use generics quite easily.
You can find sample code for each kind of RAM behavior (read first,
write first, etc.) in XST user guide.
Regards

Manu

KJ a écrit :

Hallo!

[This might be a good question for BJ, can you beat him to it?]

I would like to instantiate some Xilinx technology specific RAMs
without using the core generator wrappers. My RAM block has generics
on it to specify the size, and I would like to pass these generics
into a XilinxCoreLib component.

Usually what I do in this type of situation is let the wizard produce
their files and then hand edit the file(s) as required to add the
generics that I want to the entity that they created and then use those
generics in place of where the wizard put my numbers in.

KJ