Instantiating black box module

[Dek]

Hi all,

I'm trying to instantiate a RAM using Block-Ram with Xilinx Core
Generator. I've succesfully create the Core, and simulated it with
Modelsim (using the .vhd file created by Core Generator). Now when I
try to synthesize my design with ISE project navigator I got this
warning:

line 130: Instantiating black box module <ram_128>.

should I explicitly add the ram_128.vhd file? Or, since my design
actually do synthesize, should I just ignore this warning?

Thanks all

Dek

 

[joris]

I think you should add the ram_128.vhd file!

 

[mamu]

The .vhd is only for simulation. The CoreGen tool has also created a .ngc wich is a pre-synthesized encrypted netlist for this core.

The ISE toolchain will look for the .ngc (it should be located in your project folder or where the macro_search_path variable points to) file and include it after the synthesis step.

So yes, you can ignore this warning.

 

[Dek]

At synthesis, notice (then ignore) the warning.

At Translate, make sure it finds the implementation of ram_128 - e.g. look for a
message "Loading module ram_128.ngc" or some such in the console or the .bld
report file.

If Translate can't find it: (a) move it into the project directory or (b) set
the "core search path" option to point to the right directory.

- Brian

Thanks Brian,

during Translate I had this message:

Loading design module "ipcore_dir/ram_128.ngc"...
Applying constraints in "ipcore_dir/ram_128.ncf" to module
"ipcore_dir/ram_128.ngc"...

so it should be ok. I've asked it because I generated post place and
route simulation model and I tried to simulate it, but post layout
simulation differs from functional simulation. I thought the problem
was this of the blak box module, but if you confirm me that I can
ignore this warning I'll seek the problem somewhere else.

Thanks

Dek