Hi. I wanted to apply a user constraint file that was created using the architecture wizard in Xilinx ISE. It should work with another generated file - a vhd one that is an instance of clock divider (from 50MHz to 25MHz). However, when I want to implement it it says that no instance of a given name was found.
this is the ucf file (part):
INST DCM_INST CLKDV_DIVIDE = 2.0;
INST DCM_INST CLKFX_DIVIDE = 1;
INST DCM_INST CLKFX_MULTIPLY = 4;
and this is part of the top module of the design (vga_driver):
architecture Behavioral of vga_driver is
signal clk2 : std_logic;
COMPONENT clockdiv2
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKDV_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
begin
DCM_INST: clockdiv2 PORT MAP(
CLKIN_IN => clk,
RST_IN => reset,
CLKDV_OUT => clk2,
CLKIN_IBUFG_OUT => unused1,
CLK0_OUT => unused2,
LOCKED_OUT => unused3
);
end Behavioral;
btw: if the generated block has outputs I don't need is there a way just to 'terminate' them without applying any 'unused' signal to them?
this is the ucf file (part):
INST DCM_INST CLKDV_DIVIDE = 2.0;
INST DCM_INST CLKFX_DIVIDE = 1;
INST DCM_INST CLKFX_MULTIPLY = 4;
and this is part of the top module of the design (vga_driver):
architecture Behavioral of vga_driver is
signal clk2 : std_logic;
COMPONENT clockdiv2
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKDV_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
begin
DCM_INST: clockdiv2 PORT MAP(
CLKIN_IN => clk,
RST_IN => reset,
CLKDV_OUT => clk2,
CLKIN_IBUFG_OUT => unused1,
CLK0_OUT => unused2,
LOCKED_OUT => unused3
);
end Behavioral;
btw: if the generated block has outputs I don't need is there a way just to 'terminate' them without applying any 'unused' signal to them?